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Box" To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev, lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com, michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select hardware Date: Wed, 2 Nov 2022 19:18:18 -0700 Message-Id: <20221103021822.308586-1-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748439669456882656?= X-GMAIL-MSGID: =?utf-8?q?1748439669456882656?= This series adds a work around for enabling PCIe ASPM and for setting PCIe LTR values on VMD reserved root ports on select platforms. While configuration of these capabilities is usually done by BIOS, on these platforms these capabilities will not be configured because the ports are not visible to BIOS. This was part of an initial design that expected the driver to completely handle the ports, including power management. However on Linux those ports are still managed by the PCIe core, which has the expectation that they adhere to device standards including BIOS configuration, leading to this problem. The target platforms are Tiger Lake, Alder Lake, and Raptor Lake though the latter has already implemented support for configuring the LTR values. Meteor Lake is expected add BIOS ASPM support, eliminating the future need for this work around. Note, the driver programs the LTRs because BIOS would also normally do this for devices that do not set them by default. Without this, SoC power management would be blocked on those platform. This SoC specific value is the maximum latency required to allow the SoC to enter the deepest power state. This patch addresses the following open bugzillas on VMD enabled laptops that cannot enter low power states. Link: https://bugzilla.kernel.org/show_bug.cgi?id=212355 Link: https://bugzilla.kernel.org/show_bug.cgi?id=215063 Link: https://bugzilla.kernel.org/show_bug.cgi?id=213717 David E. Box (3): PCI: vmd: Use PCI_VDEVICE in device list PCI: vmd: Create feature grouping for client products PCI: vmd: Add quirk to configure PCIe ASPM and LTR Michael Bottini (1): PCI/ASPM: Add pci_enable_link_state() drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++---------- drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++ include/linux/pci.h | 7 +++ 3 files changed, 131 insertions(+), 26 deletions(-) base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740