Message ID | 20221101155642.52575-1-andriy.shevchenko@linux.intel.com |
---|---|
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp3063811wru; Tue, 1 Nov 2022 09:12:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7Ne8DA1X9za7JFFpD/yx2LPjW5oohcbSdVDabksZFWkbi8Z6GAWdSUzAmYJFnBo3WNwqN/ X-Received: by 2002:a17:906:5dcc:b0:78d:fb98:6f85 with SMTP id p12-20020a1709065dcc00b0078dfb986f85mr20031336ejv.123.1667319130587; Tue, 01 Nov 2022 09:12:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667319130; cv=none; d=google.com; s=arc-20160816; b=Vl5qHXhKASP3GpKVk8mFzdyvavowmuUCpQOGjR382h0EnfN8gwI7KBjNbTuQL9whEv oCgkeal0fOiiZaLO3M1wAXfkzZEOOfsbs+WXNjRnQfsn9BZ7mzX0O/2tZSUPqtF0Jpym 2YlRBt3mYqwW4htLTDf5XSxiRnmwRYXWmA4/zx2HO1cGJuXKtSVCTQaVtJq9OTDuP8J0 rYXbY+91MHs86cijjgWbtR8gCLPWwA1KdL7Vc6y2gDppnM+yxay74Fxxe0qruQr8IVli KH3py3EMPjCfukrqt6ef1WYWj5Xb5sH+PR4ZbgkfBI54N+wrUE52kVQFLCKZ+OPj6OHg HMQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=n4ply7h2G/FRSuW5UmrelLVdiKlQwrLjSVbBxnIBAww=; b=IkiMxA2kxGVzKa3/XuMkSWpruxgurzHmdfa3uP6zTFyGnmyjXrQAeNa/yqfJ8OI0rJ EY4/3maOS4BpMe7ikfNGdFYjhp0gL35stZnbDg2X4A9dcXvA1uny2nYN/kaIzGuQrxKL kUy98Vs5lL/GWXSXDquaVcnfGkWJUV+LhS1o/R3U2XEmn8hMXmtAAJ7oQqRk25dX4TPm MdPEoEfp5mcjQyIv4yaGo+cCIJVR0SWSWi3wJGHGx39AMXmS+BQPsJc8vJXSdeDbIgXC DGKmXNPD26LGLPHUrU3nBxG8aS26o4y1c1JaOCsHD7uHLFqi1BpYRVfN2Ksli8UVVSgo d6kQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="g/LIc4Zr"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w1-20020a056402268100b0045d292ef641si13103548edd.493.2022.11.01.09.11.38; Tue, 01 Nov 2022 09:12:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="g/LIc4Zr"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbiKAP4b (ORCPT <rfc822;kartikey406@gmail.com> + 99 others); Tue, 1 Nov 2022 11:56:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229462AbiKAP42 (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 1 Nov 2022 11:56:28 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAEB8381; Tue, 1 Nov 2022 08:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667318187; x=1698854187; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Rt/S8ugIyQc8CcEgszJLJMjilUawwEzDrxItMe6ZNY0=; b=g/LIc4ZrHnVTXnL99ZiFlbm2nfFiEiE/v2RnUGpJ+AjBvXUOutWM7SKY fDMS+mdXySVXn+5o2l/WABroRAakf+OQyJFUzH6LzXqwe3qLAeQWRVZqk fSsj6yZrHpl3wtOZ7Z471pUXQXl/GunZZ6AnufLTADrKLIQ29hyqvDPQ5 WxBVCEF6G2K3VadzjM5xRNApMRkSYthqQTxEcTgw2mpqRi0Pz8QAA88mA R/fo4bachhXlii2bCkLrj7TjLH8JjOulV1i4ViX+Sety3/WlKlKIGe/Hh /kYQgq1AwMotMLSRPevan3zbrfYPkDRAFvefy7K3/a6gOmvEEb9egd+jX w==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="292474804" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="292474804" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 08:56:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="776537914" X-IronPort-AV: E=Sophos;i="5.95,231,1661842800"; d="scan'208";a="776537914" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 01 Nov 2022 08:56:24 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5F6BFF7; Tue, 1 Nov 2022 17:56:47 +0200 (EET) From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Hans de Goede <hdegoede@redhat.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>, Thierry Reding <thierry.reding@gmail.com>, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Mika Westerberg <mika.westerberg@linux.intel.com>, Andy Shevchenko <andy@kernel.org>, Linus Walleij <linus.walleij@linaro.org> Subject: [PATCH v1 0/6] pinctrl: intel: Enable PWM optional feature Date: Tue, 1 Nov 2022 17:56:36 +0200 Message-Id: <20221101155642.52575-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748310824335854473?= X-GMAIL-MSGID: =?utf-8?q?1748310824335854473?= |
Series |
pinctrl: intel: Enable PWM optional feature
|
|
Message
Andy Shevchenko
Nov. 1, 2022, 3:56 p.m. UTC
This is a continuation of the previously applied PWM LPSS clean up. Now, we would like to enable PWM optional feature that may be embedded into Intel pin control IPs (starting from Sky Lake platforms). I would like to route this via Intel pin control tree with issuing an immutable branch for both PINCTRL and PWM subsystems, but I'm open for other suggestions. Hans, I dared to leave your Rb tags, however the patches are slighly differ, because of the Uwe's suggestion on how to handle the missing headers. I hope you is okay with that. If not, please comment what must be ammended then. Cc: Hans de Goede <hdegoede@redhat.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Andy Shevchenko (6): pwm: Add a stub for devm_pwmchip_add() pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: lpss: Include headers we are direct user of pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Add pwm_lpss_probe() stub pinctrl: intel: Enumerate PWM device when community has a capabilitty drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++ drivers/pwm/pwm-lpss.c | 2 +- drivers/pwm/pwm-lpss.h | 34 ++++----------- .../linux/platform_data/x86}/pwm-lpss.h | 41 ++++++++----------- include/linux/pwm.h | 5 +++ 5 files changed, 61 insertions(+), 50 deletions(-) copy {drivers/pwm => include/linux/platform_data/x86}/pwm-lpss.h (51%)
Comments
Hi Andy, On Tue, Nov 01, 2022 at 05:56:36PM +0200, Andy Shevchenko wrote: > This is a continuation of the previously applied PWM LPSS clean up. > Now, we would like to enable PWM optional feature that may be embedded > into Intel pin control IPs (starting from Sky Lake platforms). > > I would like to route this via Intel pin control tree with issuing > an immutable branch for both PINCTRL and PWM subsystems, but I'm > open for other suggestions. > > Hans, I dared to leave your Rb tags, however the patches are slighly > differ, because of the Uwe's suggestion on how to handle the missing > headers. I hope you is okay with that. If not, please comment what > must be ammended then. > > Cc: Hans de Goede <hdegoede@redhat.com> > Cc: Mika Westerberg <mika.westerberg@linux.intel.com> > > Andy Shevchenko (6): > pwm: Add a stub for devm_pwmchip_add() > pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS > pwm: lpss: Include headers we are direct user of > pwm: lpss: Allow other drivers to enable PWM LPSS > pwm: lpss: Add pwm_lpss_probe() stub > pinctrl: intel: Enumerate PWM device when community has a capabilitty Looks good to me. For the entire series, Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>