mbox series

[0/2] Add pinctrl support for S32 SoC family

Message ID 20221031100843.14579-1-clin@suse.com
Headers
Series Add pinctrl support for S32 SoC family |

Message

Chester Lin Oct. 31, 2022, 10:08 a.m. UTC 
  Hello,

Here I want to introduce a new patch series, which aims to support IOMUX
functions provided by SIUL2 [System Integration Unit Lite2] on S32 SoCs,
such as S32G2. This series is originally from NXP's implementation on
CodeAurora[1] and it will be required by upstream kernel for supporting
a variety of devices on S32 SoCs which need to config PINMUXs, such as
PHYs and MAC controllers.

Currently, the whole architecture relies on FDTs offered by ATF[3] on
CodeAurora to keep the flexibility of handling multiple S32 platforms since
now S32 clks can be triggered via the ARM SCMI clock protocol and clk IDs/
settings can vary according to different board designs. To ensure that the
driver can work properly, the dt-binding schemas in this patchset are still
required as references.

Thanks,
Chester

[1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/pinctrl/freescale?h=bsp34.0-5.10.120-rt
[2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/tag/?h=bsp34.0-2.5

Chester Lin (2):
  dt-bindings: pinctrl: add schema for NXP S32 SoCs
  pinctrl: add NXP S32 SoC family support

 .../pinctrl/nxp,s32cc-siul2-pinctrl.yaml      |   91 ++
 drivers/pinctrl/freescale/Kconfig             |   16 +
 drivers/pinctrl/freescale/Makefile            |    2 +
 drivers/pinctrl/freescale/pinctrl-s32.h       |   65 ++
 drivers/pinctrl/freescale/pinctrl-s32cc.c     | 1023 +++++++++++++++++
 drivers/pinctrl/freescale/pinctrl-s32g.c      |  759 ++++++++++++
 6 files changed, 1956 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32.h
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32cc.c
 create mode 100644 drivers/pinctrl/freescale/pinctrl-s32g.c