Message ID | 20221026190441.4002212-1-quic_molvera@quicinc.com |
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Wed, 26 Oct 2022 19:04:53 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29QJ4qHO013943 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Oct 2022 19:04:52 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 12:04:52 -0700 From: Melody Olvera <quic_molvera@quicinc.com> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org> CC: Taniya Das <quic_tdas@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Melody Olvera <quic_molvera@quicinc.com> Subject: [PATCH v3 0/5] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Date: Wed, 26 Oct 2022 12:04:36 -0700 Message-ID: <20221026190441.4002212-1-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nqAXesLAyoSbdTqmIEzlarqXGy1ShAY5 X-Proofpoint-ORIG-GUID: nqAXesLAyoSbdTqmIEzlarqXGy1ShAY5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-26_07,2022-10-26_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=839 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210260107 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747778333027189869?= X-GMAIL-MSGID: =?utf-8?q?1747778333027189869?= |
Series |
clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs
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Message
Melody Olvera
Oct. 26, 2022, 7:04 p.m. UTC
This series adds the GCC, RPMh, and PDC clock support required for the QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit 1000 are new SoCs meant for enabling Open RAN solutions. See more at https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf This patchset is based on the YAML conversion patch [1] submitted already. [1] https://lore.kernel.org/r/20220103074348.6039-1-luca.weiss@fairphone.com Changes from v2: - Revised dt-bindings - Removed qru compat strings - Updated some clocks to use clk_branch ops instead of clk_branch2 and HALT_ENABLE Melody Olvera (4): dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 Taniya Das (1): clk: qcom: Add QDU1000 and QRU1000 GCC support .../bindings/clock/qcom,gcc-qdu1000.yaml | 77 + .../bindings/clock/qcom,rpmhcc.yaml | 1 + .../interrupt-controller/qcom,pdc.yaml | 1 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 13 + drivers/clk/qcom/gcc-qdu1000.c | 2645 +++++++++++++++++ include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++ 8 files changed, 2916 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml create mode 100644 drivers/clk/qcom/gcc-qdu1000.c create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h base-commit: 60eac8672b5b6061ec07499c0f1b79f6d94311ce
Comments
On Wed, 26 Oct 2022 12:04:36 -0700, Melody Olvera wrote: > This series adds the GCC, RPMh, and PDC clock support required for the > QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. > > The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit > 1000 are new SoCs meant for enabling Open RAN solutions. See more at > https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf > > [...] Applied, thanks! [2/5] dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 commit: 70d9f589918aaadd6d5547ecb27355b7b69fc32c [4/5] clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks commit: 05e5c125b120c75b9313af0a6dc8c4f5a71e8e7c Best regards,