mbox series

[v2,0/2] Fix broken SET/CLR mode of a certain number of pins for MediaTek MT8385 SoC

Message ID 20221021084708.1109986-1-bchihi@baylibre.com
Headers
Series Fix broken SET/CLR mode of a certain number of pins for MediaTek MT8385 SoC |

Message

Balsam CHIHI Oct. 21, 2022, 8:47 a.m. UTC 
  From: Balsam CHIHI <bchihi@baylibre.com>

On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.

This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
"https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"

Changelog:
Changes in v2 :
        - Rebase on top of 6.1.0-rc1-next-20221020
        - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
        - Add mt8365_set_clr_mode() callback

Changes in v1 :
        - "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"

Balsam CHIHI (2):
  pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for
    broken SET/CLR modes
  pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback

 drivers/pinctrl/mediatek/pinctrl-mt8365.c     | 18 ++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common.h |  8 +++++++-
 3 files changed, 40 insertions(+), 1 deletion(-)

Comments

Kevin Hilman Oct. 31, 2022, 4:40 p.m. UTC | #1 
Hi Balsam,


bchihi@baylibre.com writes:

> From: Balsam CHIHI <bchihi@baylibre.com>
>
> On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
>
> This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
> "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
>
> Changelog:
> Changes in v2 :
>         - Rebase on top of 6.1.0-rc1-next-20221020
>         - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
>         - Add mt8365_set_clr_mode() callback

nit: subject of cover letter should also include "pinctrl: mediatek:"
prefix.  Also note that you're missing the word "PATCH" in all of the
subjects.

Tip: If you use `git format-patch`, you can just pass `-v2` on the
cmdline and it will create the prefixes for you automatically.

Kevin
Balsam CHIHI Nov. 2, 2022, 9:22 a.m. UTC | #2 
On Mon, Oct 31, 2022 at 5:40 PM Kevin Hilman <khilman@kernel.org> wrote:
>
> Hi Balsam,
>
>
> bchihi@baylibre.com writes:
>
> > From: Balsam CHIHI <bchihi@baylibre.com>
> >
> > On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> > To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> > This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
> >
> > This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
> > "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
> >
> > Changelog:
> > Changes in v2 :
> >         - Rebase on top of 6.1.0-rc1-next-20221020
> >         - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> >         - Add mt8365_set_clr_mode() callback
>
> nit: subject of cover letter should also include "pinctrl: mediatek:"
> prefix.  Also note that you're missing the word "PATCH" in all of the
> subjects.
>
> Tip: If you use `git format-patch`, you can just pass `-v2` on the
> cmdline and it will create the prefixes for you automatically.
>

Hi Kevin,

Well received.
I will fix these issues in the next version/resend.
Thank you so much for the review!

Balsam.

> Kevin
Linus Walleij Nov. 7, 2022, 2:44 p.m. UTC | #3 
On Fri, Oct 21, 2022 at 10:47 AM <bchihi@baylibre.com> wrote:

> From: Balsam CHIHI <bchihi@baylibre.com>
>
> On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
>
> This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
> "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
>
> Changelog:
> Changes in v2 :
>         - Rebase on top of 6.1.0-rc1-next-20221020
>         - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
>         - Add mt8365_set_clr_mode() callback

Patches applied, no need to resend for small issues.

Sorry for taking so long, I wanted some feedback from the Mediatek
maintainers but haven't heard anything, so I just applied them.

Yours,
Linus Walleij
Balsam CHIHI Nov. 16, 2022, 10:51 a.m. UTC | #4 
On Mon, Nov 7, 2022 at 3:44 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Fri, Oct 21, 2022 at 10:47 AM <bchihi@baylibre.com> wrote:
>
> > From: Balsam CHIHI <bchihi@baylibre.com>
> >
> > On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> > To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> > This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
> >
> > This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
> > "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
> >
> > Changelog:
> > Changes in v2 :
> >         - Rebase on top of 6.1.0-rc1-next-20221020
> >         - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> >         - Add mt8365_set_clr_mode() callback
>
> Patches applied, no need to resend for small issues.
>
> Sorry for taking so long, I wanted some feedback from the Mediatek
> maintainers but haven't heard anything, so I just applied them.
>

Hi Linus,

I'm sorry for the delay.
Thank you very much.

Best regards,
Balsam.

> Yours,
> Linus Walleij