Message ID | 20221014221051.7434-1-quic_molvera@quicinc.com |
---|---|
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp397743wrs; Fri, 14 Oct 2022 15:13:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5yH7P7FnjFNzy9deJxGGre+y/kv3TFJUWdx2FPmwh66rhpotV35sBBlJWq/njOxPwksBV/ X-Received: by 2002:a05:6402:8cc:b0:45c:a5c9:c0a with SMTP id d12-20020a05640208cc00b0045ca5c90c0amr5904538edz.135.1665785614876; Fri, 14 Oct 2022 15:13:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665785614; cv=none; d=google.com; s=arc-20160816; b=XdKde/p9WPN762okc3bMLw/ynmwLkMgihE2LvLhihnwvJDE/txQ2cx1HYqKaOjkWnX e70c3IJfyOEf4ST7O1asR5lTZTNW7k37xX2ihVaelXUj09bw692ZOsNUSdzhmvLFHjbJ OAzGZRiHk+5cRWza8nDb41GeI78g58mH3ZsYhuXG9exRWlQ2IOPHs3H+3zGevYTwxUAg dRj0yiPYs69mXKtqbSOGxZvmEnTmKmQYWyk9LoWrpVV1DVJelLyO2PmclPRht+QaDjcN 5iBW8MLcGB5vb5NyOCk9YXdjFhufT+K5MJek6/c6994rpCe9LPhEfnekG/ocb8QWrI+9 CMow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=TJKmgContc5J9yP+bO3coRr7Klyhzh9MViymVPMsuWM=; b=lzeTUqn8IPCo8vfj7DiHfVUntlcpulBOj9IAtmV2YYJ6z+kHfvZ0Q+ht9OfQ59ZdQD p9zlH95SdKp0gReMgRxe4blYm4hoUNNPh7mgKJ3UCveB5nELCPyX3AP7KVZUKWqSKhB6 KRG3n0J7dS2p8DbCFp21LCkcyrxrmTMDgC+QOHb0g38boPa/PzRjW+Z5bpcVyGjkEC+p 8J8gOuDDQklPf58DTZsMQJryi43MqR5kbjVz7pmhZoAYiZHpq6VYs8SebAKNUWnytLj3 2JBPBwW8tupGlaPOgTWkBWTjC3hxKw0PeUQqNvO4cYXA9PnAT9121L9X5BnvTJ8z7R2t 8Q2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TEECUlcb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k16-20020a170906971000b0078307781936si2849264ejx.359.2022.10.14.15.13.07; Fri, 14 Oct 2022 15:13:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TEECUlcb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbiJNWM3 (ORCPT <rfc822;ouuuleilei@gmail.com> + 99 others); Fri, 14 Oct 2022 18:12:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229761AbiJNWLx (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 14 Oct 2022 18:11:53 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A990F1C7120; Fri, 14 Oct 2022 15:11:39 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29EIEkIM025394; Fri, 14 Oct 2022 22:11:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=TJKmgContc5J9yP+bO3coRr7Klyhzh9MViymVPMsuWM=; b=TEECUlcbtC9E43gTZtDaqCMj0ZR5WZMSFIwkbgLdY8EPjN07Fn4ip1Syr2JPj73v99B/ X9hXzKfUufdD5aCbTVtsJau6IxLJ9Bve8Rm3hw4c9jrXfUw0RSlIlLx3viNJ+Q6nx5dt 9mThrlpkn7ASpi2ExQukmJGP5N8pPifR7pWRdZ/U4zInNdtvjOFlR9/L36DY36dKpkPO CSegHNwVRuji9ifX4BJQZLgEz11CL5nAnXiFs2ux8+R6Uhj+Y5ucDT+Ub6ik7WyIbayC 9ayzG9z23+BuNVEbTTfxlv5uMPECioI8e9YOAU9aUrtCfrYDqGS+Hf7MlpPwpXKLSbIT hw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k6mkdwmc0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Oct 2022 22:11:13 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29EMBCiE005979 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Oct 2022 22:11:12 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct 2022 15:11:01 -0700 From: Melody Olvera <quic_molvera@quicinc.com> To: Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Robin Murphy <robin.murphy@arm.com>, <linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Melody Olvera <quic_molvera@quicinc.com> Subject: [PATCH v2 0/2] Add smmu support for QDU1000/QRU1000 SoCs Date: Fri, 14 Oct 2022 15:10:49 -0700 Message-ID: <20221014221051.7434-1-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ePb0WeGlXDHEd2C5KzVDMP8x-3_z0M_6 X-Proofpoint-ORIG-GUID: ePb0WeGlXDHEd2C5KzVDMP8x-3_z0M_6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_11,2022-10-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=725 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140122 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746702817132932948?= X-GMAIL-MSGID: =?utf-8?q?1746702817132932948?= |
Series |
Add smmu support for QDU1000/QRU1000 SoCs
|
|
Message
Melody Olvera
Oct. 14, 2022, 10:10 p.m. UTC
This patchset adds smmu bindings and driver support for the QDU1000 and QRU1000 SoCs. The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit 1000 are new SoCs meant for enabling Open RAN solutions. See more at https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf Melody Olvera (2): dt-bindings: arm-smmu: Add compatible bindings for QDU1000 and QRU1000 drivers: arm-smmu-impl: Add QDU1000 and QRU1000 iommu implementation Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 2 files changed, 4 insertions(+) base-commit: dca0a0385a4963145593ba417e1417af88a7c18d
Comments
On 10/14/2022 3:10 PM, Melody Olvera wrote: > This patchset adds smmu bindings and driver support for the QDU1000 > and QRU1000 SoCs. > > The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit > 1000 are new SoCs meant for enabling Open RAN solutions. See more at > https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf Changes from v1: - fixed ordering > > Melody Olvera (2): > dt-bindings: arm-smmu: Add compatible bindings for QDU1000 and QRU1000 > drivers: arm-smmu-impl: Add QDU1000 and QRU1000 iommu implementation > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ > 2 files changed, 4 insertions(+) > > > base-commit: dca0a0385a4963145593ba417e1417af88a7c18d