mbox series

[v5,0/7] KVM: x86: Hyper-V invariant TSC control feature

Message ID 20221013095849.705943-1-vkuznets@redhat.com
Headers
Series KVM: x86: Hyper-V invariant TSC control feature |

Message

Vitaly Kuznetsov Oct. 13, 2022, 9:58 a.m. UTC 
  Changes since v4:
- s,HV_INVARIANT_TSC_EXPOSED,HV_EXPOSE_INVARIANT_TSC, [Michael]
- Add Michael's R-b to PATCH1
- Use 'KVM-only' instead of 'scattered' in PATCH2's subject [Sean, Jim]
- Do not set CPUID_8000_0007_EDX to 'NCAPINTS + 1' explicitly [Sean]
- Use the opportunity and switch to 'true'/'false' for 'msr->write'/
  'msr->fault_exepected' in 'hyperv_features' test [Sean]
- Fix HVCALL_NOTIFY_LONG_SPIN_WAIT test breakage by setting 
  HYPERV_CPUID_ENLIGHTMENT_INFO.EBX.
- "KVM: selftests: Test that values written to Hyper-V MSRs are
  preserved" patch added [Sean]

Original description:

Normally, genuine Hyper-V doesn't expose architectural invariant TSC
(CPUID.80000007H:EDX[8]) to its guests by default. A special PV MSR
(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x40000118) and corresponding CPUID
feature bit (CPUID.0x40000003.EAX[15]) were introduced. When bit 0 of the
PV MSR is set, invariant TSC bit starts to show up in CPUID. When the 
feature is exposed to Hyper-V guests, reenlightenment becomes unneeded.

Note: strictly speaking, KVM doesn't have to have the feature as exposing
raw invariant TSC bit (CPUID.80000007H:EDX[8]) also seems to work for
modern Windows versions. The feature is, however, tiny and straitforward
and gives additional flexibility so why not.

Vitaly Kuznetsov (7):
  x86/hyperv: Add HV_EXPOSE_INVARIANT_TSC define
  KVM: x86: Add a KVM-only leaf for CPUID_8000_0007_EDX
  KVM: x86: Hyper-V invariant TSC control
  KVM: selftests: Rename 'msr->available' to 'msr->fault_exepected' in
    hyperv_features test
  KVM: selftests: Convert hyperv_features test to using
    KVM_X86_CPU_FEATURE()
  KVM: selftests: Test that values written to Hyper-V MSRs are preserved
  KVM: selftests: Test Hyper-V invariant TSC control

 arch/x86/include/asm/hyperv-tlfs.h            |   3 +
 arch/x86/include/asm/kvm_host.h               |   1 +
 arch/x86/kernel/cpu/mshyperv.c                |   2 +-
 arch/x86/kvm/cpuid.c                          |  11 +-
 arch/x86/kvm/hyperv.c                         |  19 +
 arch/x86/kvm/hyperv.h                         |  27 ++
 arch/x86/kvm/reverse_cpuid.h                  |   7 +
 arch/x86/kvm/x86.c                            |   4 +-
 .../selftests/kvm/include/x86_64/hyperv.h     | 144 +++++---
 .../selftests/kvm/include/x86_64/processor.h  |   1 +
 .../selftests/kvm/x86_64/hyperv_features.c    | 330 +++++++++++-------
 11 files changed, 366 insertions(+), 183 deletions(-)

Comments

Sean Christopherson Oct. 14, 2022, 8:04 p.m. UTC | #1 
On Thu, Oct 13, 2022, Vitaly Kuznetsov wrote:
> Normally, genuine Hyper-V doesn't expose architectural invariant TSC
> (CPUID.80000007H:EDX[8]) to its guests by default. A special PV MSR
> (HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x40000118) and corresponding CPUID
> feature bit (CPUID.0x40000003.EAX[15]) were introduced. When bit 0 of the
> PV MSR is set, invariant TSC bit starts to show up in CPUID. When the 
> feature is exposed to Hyper-V guests, reenlightenment becomes unneeded.
> 
> Note: strictly speaking, KVM doesn't have to have the feature as exposing
> raw invariant TSC bit (CPUID.80000007H:EDX[8]) also seems to work for
> modern Windows versions. The feature is, however, tiny and straitforward
> and gives additional flexibility so why not.
> 
> Vitaly Kuznetsov (7):
>   x86/hyperv: Add HV_EXPOSE_INVARIANT_TSC define
>   KVM: x86: Add a KVM-only leaf for CPUID_8000_0007_EDX
>   KVM: x86: Hyper-V invariant TSC control
>   KVM: selftests: Rename 'msr->available' to 'msr->fault_exepected' in
>     hyperv_features test
>   KVM: selftests: Convert hyperv_features test to using
>     KVM_X86_CPU_FEATURE()
>   KVM: selftests: Test that values written to Hyper-V MSRs are preserved
>   KVM: selftests: Test Hyper-V invariant TSC control

For the series, in case Paolo ends up grabbing this:

Reviewed-by: Sean Christopherson <seanjc@google.com>
Vitaly Kuznetsov Nov. 22, 2022, 3:43 p.m. UTC | #2 
Sean Christopherson <seanjc@google.com> writes:

> On Thu, Oct 13, 2022, Vitaly Kuznetsov wrote:
>> Normally, genuine Hyper-V doesn't expose architectural invariant TSC
>> (CPUID.80000007H:EDX[8]) to its guests by default. A special PV MSR
>> (HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x40000118) and corresponding CPUID
>> feature bit (CPUID.0x40000003.EAX[15]) were introduced. When bit 0 of the
>> PV MSR is set, invariant TSC bit starts to show up in CPUID. When the 
>> feature is exposed to Hyper-V guests, reenlightenment becomes unneeded.
>> 
>> Note: strictly speaking, KVM doesn't have to have the feature as exposing
>> raw invariant TSC bit (CPUID.80000007H:EDX[8]) also seems to work for
>> modern Windows versions. The feature is, however, tiny and straitforward
>> and gives additional flexibility so why not.
>> 
>> Vitaly Kuznetsov (7):
>>   x86/hyperv: Add HV_EXPOSE_INVARIANT_TSC define
>>   KVM: x86: Add a KVM-only leaf for CPUID_8000_0007_EDX
>>   KVM: x86: Hyper-V invariant TSC control
>>   KVM: selftests: Rename 'msr->available' to 'msr->fault_exepected' in
>>     hyperv_features test
>>   KVM: selftests: Convert hyperv_features test to using
>>     KVM_X86_CPU_FEATURE()
>>   KVM: selftests: Test that values written to Hyper-V MSRs are preserved
>>   KVM: selftests: Test Hyper-V invariant TSC control
>
> For the series, in case Paolo ends up grabbing this:
>
> Reviewed-by: Sean Christopherson <seanjc@google.com>
>

I completely forgot about this one! Any chance it can still be queueed
for 6.2? Thanks!
Paolo Bonzini Dec. 24, 2022, 11:04 a.m. UTC | #3 
Queued, thanks.

Paolo