Message ID | 1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com |
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Fri, 19 Jan 2024 13:00:32 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0WkR023724; Fri, 19 Jan 2024 13:00:32 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0V8t023713; Fri, 19 Jan 2024 13:00:32 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 0D608273A; Fri, 19 Jan 2024 18:30:31 +0530 (+0530) From: Mrinmay Sarkar <quic_msarkar@quicinc.com> To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar <quic_msarkar@quicinc.com>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Serge Semin <fancer.lancer@gmail.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= <kw@linux.com>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Kishon Vijay Abraham I <kishon@kernel.org>, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 0/6] Add Change to integrate HDMA with dwc ep driver Date: Fri, 19 Jan 2024 18:30:16 +0530 Message-Id: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: epo6p-1FcXSHNkhTjx5fREvGlbo5I4XY X-Proofpoint-ORIG-GUID: epo6p-1FcXSHNkhTjx5fREvGlbo5I4XY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=581 clxscore=1011 suspectscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190065 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523906549404260 X-GMAIL-MSGID: 1788523906549404260 |
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Add Change to integrate HDMA with dwc ep driver
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Message
Mrinmay Sarkar
Jan. 19, 2024, 1 p.m. UTC
Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the unrolled mapping format. This patch series is to integrate HDMA with dwc ep driver. Add change to provide a valid base address of the CSRs from the platform driver and also provides read/write channels count from platform driver since there is no standard way to auto detect the number of available read/write channels in a platform and set the mapping format in platform driver for HDMA. This series passes 'struct dw_edma_chip' to irq_vector() as it needs to access that particular structure and fix to get the eDMA/HDMA max channel count. Also move the HDMA max channel definition to edma.h to maintain uniformity with eDMA. Dependency ---------- Depends on: https://lore.kernel.org/dmaengine/20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com/ https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/ Manivannan Sadhasivam (4): dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector() dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max channel count PCI: dwc: Add HDMA support dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h Mrinmay Sarkar (2): PCI: qcom-ep: Provide number of read/write channel for HDMA PCI: epf-mhi: Add flag to enable HDMA for SA8775P drivers/dma/dw-edma/dw-edma-core.c | 29 ++++++++++--- drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- drivers/dma/dw-edma/dw-hdma-v0-core.c | 4 +- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 3 +- drivers/pci/controller/dwc/pcie-designware.c | 63 ++++++++++++++++++++++------ drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + include/linux/dma/edma.h | 18 +++++++- 8 files changed, 115 insertions(+), 26 deletions(-)
Comments
Hi Mrinmay On Fri, Jan 19, 2024 at 06:30:16PM +0530, Mrinmay Sarkar wrote: > Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. > Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the > unrolled mapping format. This patch series is to integrate HDMA with > dwc ep driver. > > Add change to provide a valid base address of the CSRs from the > platform driver and also provides read/write channels count from > platform driver since there is no standard way to auto detect the > number of available read/write channels in a platform and set the > mapping format in platform driver for HDMA. > > This series passes 'struct dw_edma_chip' to irq_vector() as it needs > to access that particular structure and fix to get the eDMA/HDMA > max channel count. Also move the HDMA max channel definition to edma.h > to maintain uniformity with eDMA. Thanks for the patchset. I'll have a look at it later on this week or early on the next one. If you wish you can resubmit it by then with the Dmitry' and Mani' notes fixed. -Serge(y) > > Dependency > ---------- > Depends on: > https://lore.kernel.org/dmaengine/20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com/ > https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/ > > Manivannan Sadhasivam (4): > dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector() > dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max > channel count > PCI: dwc: Add HDMA support > dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h > > Mrinmay Sarkar (2): > PCI: qcom-ep: Provide number of read/write channel for HDMA > PCI: epf-mhi: Add flag to enable HDMA for SA8775P > > drivers/dma/dw-edma/dw-edma-core.c | 29 ++++++++++--- > drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- > drivers/dma/dw-edma/dw-hdma-v0-core.c | 4 +- > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 3 +- > drivers/pci/controller/dwc/pcie-designware.c | 63 ++++++++++++++++++++++------ > drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++- > drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + > include/linux/dma/edma.h | 18 +++++++- > 8 files changed, 115 insertions(+), 26 deletions(-) > > -- > 2.7.4 >