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Tue, 21 Nov 2023 14:38:19 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3ALEcGYx006070; Tue, 21 Nov 2023 14:38:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3uepbke7pp-1; Tue, 21 Nov 2023 14:38:16 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3ALEcGmF006065; Tue, 21 Nov 2023 14:38:16 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3ALEcFP4006064; Tue, 21 Nov 2023 14:38:16 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 9DEEE4C8C; Tue, 21 Nov 2023 20:08:14 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v4 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P Date: Tue, 21 Nov 2023 20:08:10 +0530 Message-Id: <1700577493-18538-1-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hucPD2BD1A0sKVbOd06dDvDBg8XxajXj X-Proofpoint-GUID: hucPD2BD1A0sKVbOd06dDvDBg8XxajXj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-21_07,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=333 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311210114 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 06:38:31 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783184874038474474 X-GMAIL-MSGID: 1783184874038474474 In a multiprocessor system cache snooping maintains the consistency of caches. Snooping logic is disabled from HW on this platform. Cache coherency doesn’t work without enabling this logic. This series is to enable cache snooping logic in both RC and EP driver and add the "dma-coherent" property in dtsi to support cache coherency in 8775 platform. To verify this series we required [1] [1] https://lore.kernel.org/all/1699669982-7691-1-git-send-email-quic_msarkar@quicinc.com/ v3 -> v4: - added new cfg(cfg_1_34_0) for SA8775P in both RC and EP driver. - populated a flag in the data structures instead of doing of_device_is_compatible() in both RC and EP patch. - update commit mesaage and added reveiwed-by tag in commit message in dtsi patch. v2 -> v3: - update commit message(8755 -> 8775). v1 -> v2: - update cover letter with explanation. - define each of these bits and ORing at usage time rather than directly writing value in register. Mrinmay Sarkar (3): PCI: qcom: Enable cache coherency for SA8775P RC platform PCI: qcom-ep: Enable cache coherency for SA8775P EP arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- drivers/pci/controller/dwc/pcie-qcom.c | 20 +++++++++++++++++++- 3 files changed, 42 insertions(+), 2 deletions(-) Reviewed-by: Konrad Dybcio