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Wed, 19 Jul 2023 07:20:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3rumhm1v71-1; Wed, 19 Jul 2023 07:20:20 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36J7KKdl022610; Wed, 19 Jul 2023 07:20:20 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36J7KKAn022583; Wed, 19 Jul 2023 07:20:20 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id A01AC47C7; Wed, 19 Jul 2023 12:50:19 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru Subject: [PATCH v10 0/4] PCI: qcom: ep: Add basic interconnect support Date: Wed, 19 Jul 2023 12:50:14 +0530 Message-Id: <1689751218-24492-1-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zrZncTP3iTbsVQl7qu_YnR_jtz-V1_8W X-Proofpoint-ORIG-GUID: zrZncTP3iTbsVQl7qu_YnR_jtz-V1_8W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-19_04,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxlogscore=517 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190066 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771833736789734565 X-GMAIL-MSGID: 1771833736789734565 Add basic support for managing "pcie-mem" interconnect path by setting a low constraint before enabling clocks and updating it after the link is up based on link speed and width the device got enumerated. changes from v9: - addressed the comments by mani. changes from v8: - Added cpu to pcie path in dtsi and in dtsi binding. changes from v7: - setting icc bw to '0' in disable resources as suggested by mani. changes from v6: - addressed the comments as suggested by mani. changes from v5: - addressed the comments by mani. changes from v4: - rebased with linux-next. - Added comments as suggested by mani. - removed the arm: dts: qcom: sdx55: Add interconnect path as that patch is already applied. changes from v3: - ran make DT_CHECKER_FLAGS=-m dt_binding_check and fixed errors. - Added macros in the qcom ep driver patch as suggested by Dmitry changes from v2: - changed the logic for getting speed and width as suggested by bjorn. - fixed compilation errors. Krishna chaitanya chundru (4): PCI: qcom-ep: Add ICC bandwidth voting support arm: dts: qcom: sdx65: Add PCIe EP interconnect path arm: dts: qcom: sdx55: Add CPU PCIe EP interconnect path dt-bindings: PCI: qcom: ep: Add interconnects path .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++ arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 71 ++++++++++++++++++++++ 4 files changed, 93 insertions(+), 2 deletions(-)