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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2023 19:44:37.0831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2aa14db-ddc6-4246-1b8f-08db6d0fc943 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4113 X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, SUBJ_ALL_CAPS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768709186982209828?= X-GMAIL-MSGID: =?utf-8?q?1768709186982209828?= Hello, The QDMA subsystem is used in conjunction with the PCI Express IP block to provide high performance data transfer between host memory and the card's DMA subsystem. +-------+ +-------+ +-----------+ PCIe | | | | | | Tx/Rx | | | | AXI | | <=======> | PCIE | <===> | QDMA | <====>| User Logic| | | | | | | +-------+ +-------+ +-----------+ Comparing to AMD/Xilinx XDMA subsystem, https://lore.kernel.org/lkml/Y+XeKt5yPr1nGGaq@matsya/ the QDMA subsystem is a queue based, configurable scatter-gather DMA implementation which provides thousands of queues, support for multiple physical/virtual functions with single-root I/O virtualization (SR-IOV), and advanced interrupt support. In this mode the IP provides AXI4-MM and AXI4-Stream user interfaces which may be configured on a per-queue basis. The QDMA has been used for Xilinx Alveo PCIe devices. https://www.xilinx.com/applications/data-center/v70.html This patch series is to provide the platform driver for AMD QDMA subsystem to support AXI4-MM DMA transfers. More functions, such as AXI4-Stream and SR-IOV, will be supported by future patches. The device driver for any FPGA based PCIe device which leverages QDMA can call the standard dmaengine APIs to discover and use the QDMA subsystem without duplicating the QDMA driver code in its own driver. Changes since v1: - Minor changes from code review comments. - Fixed kernel robot warning. Nishad Saraf (1): dmaengine: amd: qdma: Add AMD QDMA driver MAINTAINERS | 9 + drivers/dma/Kconfig | 13 + drivers/dma/Makefile | 1 + drivers/dma/amd/Makefile | 8 + drivers/dma/amd/qdma-comm-regs.c | 66 ++ drivers/dma/amd/qdma.c | 1189 ++++++++++++++++++++++++ drivers/dma/amd/qdma.h | 269 ++++++ include/linux/platform_data/amd_qdma.h | 36 + 8 files changed, 1591 insertions(+) create mode 100644 drivers/dma/amd/Makefile create mode 100644 drivers/dma/amd/qdma-comm-regs.c create mode 100644 drivers/dma/amd/qdma.c create mode 100644 drivers/dma/amd/qdma.h create mode 100644 include/linux/platform_data/amd_qdma.h