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[8.43.85.97]) by mx.google.com with ESMTPS id d17-20020aa7d691000000b004acce6608c7si2781024edr.451.2023.02.16.23.38.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 23:38:03 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="TiZi2/lw"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4654A3857835 for ; Fri, 17 Feb 2023 07:38:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4654A3857835 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1676619482; bh=nfFI19vER5bBud9sft8LXRjd7YU/LgfkcFpTRDY+6bA=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=TiZi2/lwvsumSaf3IvWyO2A/NFuwC11uf1GrS+a9Jsb0zwiGvP9JIDl7kTZmgyCss /E4CKyJXKrfj7aP6+3t+JCPp9NmTOACItIE+VibHg5OjIIa5d0RbF2tGRKyOgHclz9 G+W9ldtM2eNaLrW1Y9Vx8xkZNyVEGyP7CJdBrqeE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from rock.gnat.com (rock.gnat.com [205.232.38.15]) by sourceware.org (Postfix) with ESMTPS id 49434385B51A for ; Fri, 17 Feb 2023 07:36:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 49434385B51A Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 1DEBC116B6A; Fri, 17 Feb 2023 02:36:34 -0500 (EST) X-Virus-Scanned: Debian amavisd-new at gnat.com Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id LX1CmOOUVFMI; Fri, 17 Feb 2023 02:36:34 -0500 (EST) Received: from free.home (tron.gnat.com [IPv6:2620:20:4000:0:46a8:42ff:fe0e:e294]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by rock.gnat.com (Postfix) with ESMTPS id BF7E9116B59; Fri, 17 Feb 2023 02:36:32 -0500 (EST) Received: from livre (livre.home [172.31.160.2]) by free.home (8.15.2/8.15.2) with ESMTPS id 31H7a5fn092235 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 17 Feb 2023 04:36:06 -0300 To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, richard.earnshaw@arm.com, ramana.gcc@gmail.com, kyrylo.tkachov@arm.com, andrea.corallo@arm.com Subject: [PATCH] [arm] complete vmsr/vmrs blank and case adjustments Organization: Free thinker, does not speak for AdaCore Date: Fri, 17 Feb 2023 04:36:05 -0300 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alexandre Oliva via Gcc-patches From: Alexandre Oliva Reply-To: Alexandre Oliva Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758062951454859757?= X-GMAIL-MSGID: =?utf-8?q?1758062951454859757?= Back in September last year, some of the vmsr and vmrs patterns had an extraneous blank removed, and the case of register names lowered, but another instance remained, and so did a few testcases. Regstrapped on x86_64-linux-gnu. Tested on arm-vxworks7 (gcc-12) and arm-eabi (trunk). Ok to install? for gcc/ChangeLog * config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab after vmsr and vmrs, and lower the case of P0. for gcc/testsuite/ChangeLog * gcc.target/arm/acle/cde-mve-full-assembly.c: Drop blank after tab after vmsr, and lower the case of P0. --- gcc/config/arm/vfp.md | 4 .../gcc.target/arm/acle/cde-mve-full-assembly.c | 264 ++++++++++---------- 2 files changed, 134 insertions(+), 134 deletions(-) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index f34f35e1185e2..60e7ba35d8b25 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -312,9 +312,9 @@ (define_insn "*thumb2_movsi_vfp" case 12: case 13: return output_move_vfp (operands); case 14: - return \"vmsr\\t P0, %1\"; + return \"vmsr\\tp0, %1\"; case 15: - return \"vmrs\\t %0, P0\"; + return \"vmrs\\t%0, p0\"; case 16: return \"mcr\\tp10, 7, %1, cr1, cr0, 0\\t @SET_FPSCR\"; case 17: diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c index d025c3391fbe5..72f330185944a 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c +++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-full-assembly.c @@ -534,80 +534,80 @@ contain back references). */ /* ** test_cde_vcx1q_mfloat16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mfloat32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint8x16_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_muint64x2_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint8x16_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1q_mint64x2_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1t p0, q0, #32 ** bx lr @@ -616,80 +616,80 @@ /* ** test_cde_vcx1qa_mfloat16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mfloat32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint8x16_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_muint64x2_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint8x16_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint16x8_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint32x4_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr */ /* ** test_cde_vcx1qa_mint64x2_tintint: -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) -** (?:vmov\.i32 q0, #0 @ v16qi|vmsr P0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) +** (?:vmov\.i32 q0, #0 @ v16qi|vmsr p0, r2 @ movhi) ** vpst ** vcx1at p0, q0, #32 ** bx lr @@ -698,8 +698,8 @@ /* ** test_cde_vcx2q_mfloat16x8_tuint16x8_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -707,8 +707,8 @@ */ /* ** test_cde_vcx2q_mfloat16x8_tfloat32x4_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -716,8 +716,8 @@ */ /* ** test_cde_vcx2q_mfloat32x4_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -725,8 +725,8 @@ */ /* ** test_cde_vcx2q_mint64x2_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -734,8 +734,8 @@ */ /* ** test_cde_vcx2q_mint8x16_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -743,8 +743,8 @@ */ /* ** test_cde_vcx2q_muint16x8_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -752,8 +752,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tint64x2_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -761,8 +761,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -770,8 +770,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tuint16x8_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -779,8 +779,8 @@ */ /* ** test_cde_vcx2q_muint8x16_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2t p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -790,8 +790,8 @@ /* ** test_cde_vcx2qa_mfloat16x8_tuint16x8_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -799,8 +799,8 @@ */ /* ** test_cde_vcx2qa_mfloat16x8_tfloat32x4_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -808,8 +808,8 @@ */ /* ** test_cde_vcx2qa_mfloat32x4_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -817,8 +817,8 @@ */ /* ** test_cde_vcx2qa_mint64x2_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -826,8 +826,8 @@ */ /* ** test_cde_vcx2qa_mint8x16_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -835,8 +835,8 @@ */ /* ** test_cde_vcx2qa_muint16x8_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -844,8 +844,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tint64x2_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -853,8 +853,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -862,8 +862,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tuint16x8_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -871,8 +871,8 @@ */ /* ** test_cde_vcx2qa_muint8x16_tuint8x16_tint: -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) -** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr P0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) +** (?:vmov\.i32 q[1-7], #0 @ v16qi|vmsr p0, r1 @ movhi) ** vpst ** vcx2at p0, (q[1-7]), q0, #32 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -882,8 +882,8 @@ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -891,8 +891,8 @@ */ /* ** test_cde_vcx3q_mfloat16x8_tfloat16x8_tfloat16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -900,8 +900,8 @@ */ /* ** test_cde_vcx3q_mfloat32x4_tuint64x2_tfloat16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -909,8 +909,8 @@ */ /* ** test_cde_vcx3q_muint16x8_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -918,8 +918,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint16x8_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -927,8 +927,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tuint16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -936,8 +936,8 @@ */ /* ** test_cde_vcx3q_mint8x16_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -945,8 +945,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -954,8 +954,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -963,8 +963,8 @@ */ /* ** test_cde_vcx3q_mint64x2_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -972,8 +972,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint64x2_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -981,8 +981,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tuint8x16_tint64x2_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -990,8 +990,8 @@ */ /* ** test_cde_vcx3q_muint8x16_tint64x2_tint64x2_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3t p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1001,8 +1001,8 @@ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1010,8 +1010,8 @@ */ /* ** test_cde_vcx3qa_mfloat16x8_tfloat16x8_tfloat16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1019,8 +1019,8 @@ */ /* ** test_cde_vcx3qa_mfloat32x4_tuint64x2_tfloat16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1028,8 +1028,8 @@ */ /* ** test_cde_vcx3qa_muint16x8_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1037,8 +1037,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint16x8_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1046,8 +1046,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tuint16x8_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1055,8 +1055,8 @@ */ /* ** test_cde_vcx3qa_mint8x16_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1064,8 +1064,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1073,8 +1073,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1082,8 +1082,8 @@ */ /* ** test_cde_vcx3qa_mint64x2_tuint8x16_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1091,8 +1091,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint64x2_tuint8x16_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1100,8 +1100,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tuint8x16_tint64x2_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)? @@ -1109,8 +1109,8 @@ */ /* ** test_cde_vcx3qa_muint8x16_tint64x2_tint64x2_t: -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) -** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr P0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) +** (?:vmov\.i32 q[2-7], #0 @ v16qi|vmsr p0, r0 @ movhi) ** vpst ** vcx3at p0, (q[2-7]), q0, q1, #15 ** vmov q0, \1([[:space:]]+@ [^\n]*)?