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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id et13-20020a056402378d00b0045829a1c0b3si1030067edb.251.2022.09.29.03.43.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Sep 2022 03:43:12 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=R7JKEAgs; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EB7653853574 for ; Thu, 29 Sep 2022 10:41:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EB7653853574 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1664448100; bh=XTSlm4WxA6/O8URGQRvZN55wtC7FIToBZw1SOExjadM=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=R7JKEAgs0aATC5rYoHt33+V/3Q7wi98LPATMeeVoSEvKih/5YZQfKdsY33jXCBmBF xUU9eoPzSe0+3UY27J3QLR0bN0uNMC+OnQGw1D2P8ajIf2EWNsOPvma7yfOHSEGJpA TVLDvvHEhwB64tYNO2YFQnRxLK2jERJU1tFLY+aw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 8C9313857404 for ; Thu, 29 Sep 2022 10:40:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8C9313857404 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E835315BF for ; Thu, 29 Sep 2022 03:41:01 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.98.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E25903F73B for ; Thu, 29 Sep 2022 03:40:54 -0700 (PDT) To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 07/17] aarch64: Remove AARCH64_FL_RCPC8_4 [PR107025] References: Date: Thu, 29 Sep 2022 11:40:53 +0100 In-Reply-To: (Richard Sandiford's message of "Thu, 29 Sep 2022 11:39:11 +0100") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-46.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745300427604232415?= X-GMAIL-MSGID: =?utf-8?q?1745300427604232415?= AARCH64_FL_RCPC8_4 is an odd-one-out in that it has no associated entry in aarch64-option-extensions.def. This means that, although it is internally separated from AARCH64_FL_V8_4A, there is no mechanism for turning it on and off individually, independently of armv8.4-a. The only place that the flag was used independently was in the entry for thunderx3t110, which enabled it alongside V8_3A. As noted in PR107025, this means that any use of the extension will fail to assemble. In the PR trail, Andrew suggested removing the core entry. That might be best long-term, but since the barrier for removing command-line options without a deprecation period is very high, this patch instead just drops the flag from the core entry. We'll still produce correct code. gcc/ PR target/107025 * config/aarch64/aarch64.h (oAARCH64_FL_RCPC8_4): Delete. (AARCH64_FL_FOR_V8_4A): Update accordingly. (AARCH64_ISA_RCPC8_4): Use AARCH64_FL_V8_4A directly. * config/aarch64/aarch64-cores.def (thunderx3t110): Remove AARCH64_FL_RCPC8_4. --- gcc/config/aarch64/aarch64-cores.def | 2 +- gcc/config/aarch64/aarch64.h | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 008b0b8c177..cf500d0a981 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -133,7 +133,7 @@ AARCH64_CORE("tsv110", tsv110, tsv110, V8_2A, AARCH64_FL_CRYPTO | AARCH64_FL_F /* ARMv8.3-A Architecture Processors. */ /* Marvell cores (TX3). */ -AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, V8_3A, AARCH64_FL_CRYPTO | AARCH64_FL_RCPC | AARCH64_FL_SM4 | AARCH64_FL_SHA3 | AARCH64_FL_F16FML | AARCH64_FL_RCPC8_4, thunderx3t110, 0x43, 0x0b8, 0x0a) +AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, V8_3A, AARCH64_FL_CRYPTO | AARCH64_FL_RCPC | AARCH64_FL_SM4 | AARCH64_FL_SHA3 | AARCH64_FL_F16FML, thunderx3t110, 0x43, 0x0b8, 0x0a) /* ARMv8.4-A Architecture Processors. */ diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index c275548b18e..8ea8e2a3913 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -173,7 +173,6 @@ #define AARCH64_FL_SM4 (1 << 17) /* Has ARMv8.4-A SM3 and SM4. */ #define AARCH64_FL_SHA3 (1 << 18) /* Has ARMv8.4-a SHA3 and SHA512. */ #define AARCH64_FL_F16FML (1 << 19) /* Has ARMv8.4-a FP16 extensions. */ -#define AARCH64_FL_RCPC8_4 (1 << 20) /* Has ARMv8.4-a RCPC extensions. */ /* Statistical Profiling extensions. */ #define AARCH64_FL_PROFILE (1 << 21) @@ -265,7 +264,7 @@ (AARCH64_FL_FOR_V8_2A | AARCH64_FL_V8_3A | AARCH64_FL_PAUTH) #define AARCH64_FL_FOR_V8_4A \ (AARCH64_FL_FOR_V8_3A | AARCH64_FL_V8_4A | AARCH64_FL_F16FML \ - | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4 | AARCH64_FL_FLAGM) + | AARCH64_FL_DOTPROD | AARCH64_FL_FLAGM) #define AARCH64_FL_FOR_V8_5A \ (AARCH64_FL_FOR_V8_4A | AARCH64_FL_V8_5A \ | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES) @@ -313,7 +312,7 @@ #define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) #define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) #define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) -#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4) +#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_V8_4A) #define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) #define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) #define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)