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[8.43.85.97]) by mx.google.com with ESMTPS id lb29-20020a056214319d00b0066d009ba425si7692066qvb.43.2023.11.07.07.24.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 07:24:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 448D638582A3 for ; Tue, 7 Nov 2023 15:24:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id DC66B3856DF2 for ; Tue, 7 Nov 2023 15:24:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC66B3856DF2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DC66B3856DF2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699370644; cv=none; b=Vun9IpTRGUp5Zdg4TTkHoLcejFmUQFeOtl8+vXoAdwlxSkcHNUw+jOxPkri9FFmoWHd4pydeATH7LXPevvK68Xop+wtGW/Zq3vs6wLgWP6Zd5KkynrzM/6SfqZiaIC8LB4pXv2co4hbDo9maZOWugFvSMo/ar58Qsl2zCEgF+o8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699370644; c=relaxed/simple; bh=V+7qygC2rxs0Y8skyoIIDiw2dtJ6b1j5DFzeC7Yoar0=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=S+qLGMDPSnh0CBzJ1R0bzDX82YWOhFYh6NCI0Pm05DX6yckJFVmdhhyqdScquZDd+h2RZ9SM+xLFY5X268c/sF0HzkvY5DX8ooT/Y577c1GpzaqntjGZd5wWyralEi/wNtp2eTaSh50WT5G0qRYEfnA5QL5h7z4YfxygFdmiX4k= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 268EE1476; Tue, 7 Nov 2023 07:24:46 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E7F6B3F703; Tue, 7 Nov 2023 07:24:00 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, tamar.christina@arm.com, richard.sandiford@arm.com Cc: tamar.christina@arm.com Subject: [pushed] aarch64: Add a %Z operand modifier for SVE registers Date: Tue, 07 Nov 2023 15:23:59 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-23.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781919295488883229 X-GMAIL-MSGID: 1781919295488883229 This patch adds a %Z operand modifier that prints registers as SVE z registers. The SME patches need this, but so do Tamar's patches. I'm separating this out to unblock those. We should probably document the [wxbhsdqZ] modifiers as user-facing, but doing that for all of them is a separate patch. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_print_operand): Add a %Z modifier for SVE registers. --- gcc/config/aarch64/aarch64.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index cb65ccc8465..968a9ac439d 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -12091,6 +12091,10 @@ sizetochar (int size) 'N': Take the duplicated element in a vector constant and print the negative of it in decimal. 'b/h/s/d/q': Print a scalar FP/SIMD register name. + 'Z': Same for SVE registers. ('z' was already taken.) + Note that it is not necessary to use %Z for operands + that have SVE modes. The convention is to use %Z + only for non-SVE (or potentially non-SVE) modes. 'S/T/U/V': Print a FP/SIMD register name for a register list. The register printed is the FP/SIMD register name of X + 0/1/2/3 for S/T/U/V. @@ -12263,6 +12267,8 @@ aarch64_print_operand (FILE *f, rtx x, int code) case 's': case 'd': case 'q': + case 'Z': + code = TOLOWER (code); if (!REG_P (x) || !FP_REGNUM_P (REGNO (x))) { output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);