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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d6-20020a05621416c600b00649089daebasi6802108qvz.237.2023.10.24.03.00.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 03:00:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9BF603858436 for ; Tue, 24 Oct 2023 10:00:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B64303858C01 for ; Tue, 24 Oct 2023 10:00:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B64303858C01 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B64303858C01 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698141630; cv=none; b=knNJk9UcDfVe9E+N/gZHpGOQlMcgGDfJMyX+6s/SQMeNA3EbZ9hqbrvFk0YJMD2SGIl9I2wNWhgL37wNBcK+DxKSuHVNP0GCrIJ4jHKGkp/soLFrLgCnqAXGchQo7Oy4LQoQ6aQGIxpT942J2sTGR/NnrK5by+Lo3QnKRbIEn4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698141630; c=relaxed/simple; bh=HpYMnehHvybMwPPWz4k866ZvcqdfZLX8Qk/uOt0zsG4=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Ykoh07ResNtqLgPyNcECvz/Ame5ZZZq5vI792sXFfrNfFatL7IrKLx394OnlroK7WP2W0fyoweY3VuiydB/f/9OPAaYSEHu5TLDjcq1nMAzAFfdoxFfVGHwnjH8+cgKpKpu8F/JO2bxg1c1FAJqxR6hKAdaelzE060nWP3vUaPE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 712412F4 for ; Tue, 24 Oct 2023 03:01:09 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1E0A13F64C for ; Tue, 24 Oct 2023 03:00:28 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Define TARGET_INSN_COST Date: Tue, 24 Oct 2023 11:00:26 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-23.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780630581735034434 X-GMAIL-MSGID: 1780630581735034434 This patch adds a bare-bones TARGET_INSN_COST. See the comment in the patch for the rationale. This change is needed to avoid a regression with a later change. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_insn_cost): New function. (TARGET_INSN_COST): Define. --- gcc/config/aarch64/aarch64.cc | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index a28b66acf6a..4cbfa42cb3c 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -15541,6 +15541,28 @@ aarch64_memory_move_cost (machine_mode mode, reg_class_t rclass_i, bool in) : aarch64_tune_params.memmov_cost.store_int); } +/* Implement TARGET_INSN_COST. We have the opportunity to do something + much more productive here, such as using insn attributes to cost things. + But we don't, not yet. + + The main point of this current definition is to make calling insn_cost + on one instruction equivalent to calling seq_cost on a sequence that + contains only that instruction. The default definition would instead + only look at SET_SRCs, ignoring SET_DESTs. + + This ensures that, for example, storing a 128-bit zero vector is more + expensive than storing a 128-bit vector register. A move of zero + into a 128-bit vector register followed by multiple stores of that + register is then cheaper than multiple stores of zero (which would + use STP of XZR). This in turn allows STPs to be formed. */ +static int +aarch64_insn_cost (rtx_insn *insn, bool speed) +{ + if (rtx set = single_set (insn)) + return set_rtx_cost (set, speed); + return pattern_cost (PATTERN (insn), speed); +} + /* Implement TARGET_INIT_BUILTINS. */ static void aarch64_init_builtins () @@ -28399,6 +28421,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper +#undef TARGET_INSN_COST +#define TARGET_INSN_COST aarch64_insn_cost + #undef TARGET_SCALAR_MODE_SUPPORTED_P #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p