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[8.43.85.97]) by mx.google.com with ESMTPS id b10-20020ac844ca000000b0042377597590si6254957qto.379.2023.12.10.11.55.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Dec 2023 11:55:14 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D7A233858D32 for ; Sun, 10 Dec 2023 19:55:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7F37D3858002 for ; Sun, 10 Dec 2023 19:54:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7F37D3858002 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7F37D3858002 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702238091; cv=none; b=S07mJKQfgk3l5wq2PeF7RR6e+WAEZmsr4toulkUWK5CPGOUCcDZgicOYHwG+8wimHweEfnZeugn4fapZ75UVJ4Exocr8Oy6k3gx/ARZtaFbNTw+ezGOR3OcD2GaAQKo00mi4eqUltGH3TnWgiDE43HJiiBMDpSs5/un/OOhir8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702238091; c=relaxed/simple; bh=/NhtQI3F8+tUaBej+2ukOJdER//YFzqVnVahJ9tT/Uc=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=P/JVGYLe2T6ZbwhsMjF2/605gnSaScDJ7bzFqikZULoI+RNKFEm2rT8f6RglTWpQYWtsxJ1jZc5Aiif77nzVj2OIbAn+RNwgahO+2r2C1oUwsc1T+xWGjv55HjebC8MceQKmc/zSvveGeAsv3f2MFIq7uStLAVze/yr8NchBIfw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5DADFFEC for ; Sun, 10 Dec 2023 11:55:36 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D850F3F738 for ; Sun, 10 Dec 2023 11:54:49 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [pushed] aarch64: Fix SMSTART/SMSTOP save/restore for BE Date: Sun, 10 Dec 2023 19:54:48 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-21.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784926032761681705 X-GMAIL-MSGID: 1784926032761681705 VNx16QI (the SVE register byte mode) is the only SVE mode for which LD1 and LDR result in the same register layout for big-endian. It is therefore the only mode for which we allow LDR and STR to be used for big-endian SVE moves. The SME support sometimes needs to use LDR and STR to save and restore Z register contents around an SMSTART/SMSTOP SM. It therefore needs to use VNx16QI regardless of the type of value that is stored in the Z registers. Tested on aarch64-linux-gnu and aarch64_be-elf, pushed to trunk. Richard gcc/ PR target/112930 * config/aarch64/aarch64.cc (aarch64_sme_mode_switch_regs::add_reg): Force specific SVE modes for single registers as well as structures. --- gcc/config/aarch64/aarch64.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 5cffdabc62e..2a64053f675 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -4956,14 +4956,17 @@ aarch64_sme_mode_switch_regs::add_reg (machine_mode mode, unsigned int regno) gcc_assert ((vec_flags & VEC_STRUCT) || end_regno == regno + 1); for (; regno < end_regno; regno++) { + /* Force the mode of SVE saves and restores even for single registers. + This is necessary because big-endian targets only allow LDR Z and + STR Z to be used with byte modes. */ machine_mode submode = mode; - if (vec_flags & VEC_STRUCT) + if (vec_flags & VEC_SVE_PRED) + submode = VNx16BImode; + else if (vec_flags & VEC_SVE_DATA) + submode = SVE_BYTE_MODE; + else if (vec_flags & VEC_STRUCT) { - if (vec_flags & VEC_SVE_PRED) - submode = VNx16BImode; - else if (vec_flags & VEC_SVE_DATA) - submode = SVE_BYTE_MODE; - else if (vec_flags & VEC_PARTIAL) + if (vec_flags & VEC_PARTIAL) submode = V8QImode; else submode = V16QImode;