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[8.43.85.97]) by mx.google.com with ESMTPS id g19-20020ac85813000000b0041cb3f5c424si1950170qtg.722.2023.11.17.09.39.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 09:39:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C4A338708E4 for ; Fri, 17 Nov 2023 17:39:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 398323882064 for ; Fri, 17 Nov 2023 17:38:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 398323882064 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 398323882064 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700242736; cv=none; b=g+uw2Mksu5d3amc75UoG9JearufWawQ2NXFuJfR0UxIEd8wIgzdKkbjpiBkgrgZrL9Bl1XWCwVU30bjryw3vlwU+C2QuF0gLWZlWSormu/YZgY3NfNpKyMonxOzInEnophDh9rZtcgUn/4U3O0lRaDyPLrN0mb3ZhttQfkXfblY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700242736; c=relaxed/simple; bh=8exl5TZbpQ33w1EKNuNvAycdbtnqJ2zNbJCCsUoRsqM=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=JC7WFDF5w+fHc1yK+Zu2LYKhQIDc5jmNCVyzNSTMR0qEUfj0TvSPdBFbQIyA/EBvlQYLnTPw1t+5FCqf29NX5wJtEaiiy2yMEM6ZHw5aLcukWZWY0eDihdp2CQlKdApyHyuN+b0NT2K/QMJ9wLwYkhQxNfjtb8SjpuNvSAZh6E0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 174D91477 for ; Fri, 17 Nov 2023 09:39:41 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A6E043F73F for ; Fri, 17 Nov 2023 09:38:54 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH 1/5] aarch64: Add +sme2 Date: Fri, 17 Nov 2023 17:38:53 +0000 In-Reply-To: (Richard Sandiford's message of "Fri, 17 Nov 2023 17:37:53 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-22.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782833751386046112 X-GMAIL-MSGID: 1782833751386046112 gcc/ * doc/invoke.texi: Document +sme2. * doc/sourcebuild.texi: Document aarch64_sme2. * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION): Add sme2. * config/aarch64/aarch64.h (AARCH64_ISA_SME2, TARGET_SME2): New macros. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_aarch64_sme2): New target test. (check_effective_target_aarch64_asm_sme2_ok): Likewise. --- gcc/config/aarch64/aarch64-option-extensions.def | 2 ++ gcc/config/aarch64/aarch64.h | 4 ++++ gcc/doc/invoke.texi | 3 ++- gcc/doc/sourcebuild.texi | 2 ++ gcc/testsuite/lib/target-supports.exp | 14 +++++++++++++- 5 files changed, 23 insertions(+), 2 deletions(-) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 1480e498bbb..c156d2ee76a 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -157,4 +157,6 @@ AARCH64_OPT_EXTENSION("sme-i16i64", SME_I16I64, (SME), (), (), "") AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "") +AARCH64_OPT_EXTENSION("sme2", SME2, (SME), (), (), "sme2") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 9f690809e79..14205ce34b3 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -227,6 +227,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME) #define AARCH64_ISA_SME_I16I64 (aarch64_isa_flags & AARCH64_FL_SME_I16I64) #define AARCH64_ISA_SME_F64F64 (aarch64_isa_flags & AARCH64_FL_SME_F64F64) +#define AARCH64_ISA_SME2 (aarch64_isa_flags & AARCH64_FL_SME2) #define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) #define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) #define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) @@ -332,6 +333,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; /* The FEAT_SME_F64F64 extension to SME, enabled through +sme-f64f64. */ #define TARGET_SME_F64F64 (AARCH64_ISA_SME_F64F64) +/* SME2 instructions, enabled through +sme2. */ +#define TARGET_SME2 (AARCH64_ISA_SME2) + /* ARMv8.3-A features. */ #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index bc56170aadb..475244bb4ff 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21065,7 +21065,8 @@ Enable the Scalable Matrix Extension. Enable the FEAT_SME_I16I64 extension to SME. @item sme-f64f64 Enable the FEAT_SME_F64F64 extension to SME. - ++@item sme2 +Enable the Scalable Matrix Extension 2. This also enables SME instructions. @end table Feature @option{crypto} implies @option{aes}, @option{sha2}, and @option{simd}, diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 448f5e08578..8d8d21f9fee 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2318,6 +2318,8 @@ Binutils installed on test system supports relocation types required by -fpic for AArch64 small memory model. @item aarch64_sme AArch64 target that generates instructions for SME. +@item aarch64_sme2 +AArch64 target that generates instructions for SME2. @item aarch64_sve_hw AArch64 target that is able to generate and execute SVE code (regardless of whether it does so by default). diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b9061e5a552..87ee26f9119 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4425,6 +4425,18 @@ proc check_effective_target_aarch64_sme { } { }] } +# Return 1 if this is an AArch64 target that generates instructions for SME. +proc check_effective_target_aarch64_sme2 { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_no_compiler_messages aarch64_sme2 assembly { + #if !defined (__ARM_FEATURE_SME2) + #error FOO + #endif + }] +} + # Return 1 if this is a compiler supporting ARC atomic operations proc check_effective_target_arc_atomic { } { return [check_no_compiler_messages arc_atomic assembly { @@ -11621,7 +11633,7 @@ proc check_effective_target_aarch64_tiny { } { foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve" "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" - "sme" "sme-i16i64" } { + "sme" "sme-i16i64" "sme2" } { eval [string map [list FUNC $aarch64_ext] { proc check_effective_target_aarch64_asm_FUNC_ok { } { if { [istarget aarch64*-*-*] } {