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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id g3-20020a05620a40c300b0077f0a9abdb6si339392qko.101.2023.12.03.02.13.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Dec 2023 02:13:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F3D933858425 for ; Sun, 3 Dec 2023 10:13:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 02B273858000 for ; Sun, 3 Dec 2023 10:13:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 02B273858000 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 02B273858000 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701598388; cv=none; b=WjiV94pSEiXUIG9Xr+7nA8QOoL6trSwdfNNreIzCh85Ruo76xwy8YjLKpcVc7/TTTSAiQ9QF/wkZzHY/78iBXutQfelTP9YpHVne+no4hispVfaCuxuQx1vXP2hD99q32lV/dTTJODOxWmbiOpkZRP9fphgkD0NtVbs4IlQZFRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701598388; c=relaxed/simple; bh=3H/Xn2K7rkvE88GpYWTnXLhrwdbQL3KesCjU8RnylYY=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=uYtUlSfozqQyTeVUdhGBrSA3uSrvOQFSeIQuBSR6hiujQxn1X4mfrzpK+VBZjPRf/BsPILRJUL4Sy1Kan/0GRRIGfzFpvGP9ccQtAHZxdmdx0q6ioPqOSv2eqTge+yQy6JNutfNV/SncRz6mqX7ihFCa3fEmyyOQOYlVzsGCBIY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 185D61684; Sun, 3 Dec 2023 02:13:53 -0800 (PST) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D499F3F5A1; Sun, 3 Dec 2023 02:13:05 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, vmakarov@redhat.com, richard.sandiford@arm.com Cc: vmakarov@redhat.com Subject: [PATCH] lra: Updates of biggest mode for hard regs [PR112278] Date: Sun, 03 Dec 2023 10:13:04 +0000 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-22.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784255256694712712 X-GMAIL-MSGID: 1784255256694712712 [Gah. In my head I'd sent this a few weeks ago, but it turns out that I hadn't even got to the stage of writing the changlog...] LRA keeps track of the biggest mode for both hard registers and pseudos. The updates assume that the modes are ordered, i.e. that we can tell whether one is no bigger than the other at compile time. That is (or at least seemed to be) a reasonable restriction for pseudos. But it isn't necessarily so for hard registers, since the uses of hard registers can be logically distinct. The testcase is an example of this. The biggest mode of hard registers is also special for other reasons. As the existing comment says: /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as part of a multi-word register. In that case, just use the reg_rtx mode. Do the same also if the biggest mode was larger than a register or we can not compare the modes. Otherwise, limit the size to that of the biggest access in the function or to the natural mode at least. */ This patch applies the same approach to the updates. Tested on aarch64-linus-gnu (with and without SVE) and on x86_64-linux-gnu. OK to install? Richard gcc/ PR rtl-optimization/112278 * lra-int.h (lra_update_biggest_mode): New function. * lra-coalesce.cc (merge_pseudos): Use it. * lra-lives.cc (process_bb_lives): Likewise. * lra.cc (new_insn_reg): Likewise. gcc/testsuite/ PR rtl-optimization/112278 * gcc.target/aarch64/sve/pr112278.c: New test. --- gcc/lra-coalesce.cc | 4 +--- gcc/lra-int.h | 15 +++++++++++++++ gcc/lra-lives.cc | 4 +--- gcc/lra.cc | 5 ++--- gcc/testsuite/gcc.target/aarch64/sve/pr112278.c | 15 +++++++++++++++ 5 files changed, 34 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr112278.c diff --git a/gcc/lra-coalesce.cc b/gcc/lra-coalesce.cc index 04a5bbd714b..d8ca096c35f 100644 --- a/gcc/lra-coalesce.cc +++ b/gcc/lra-coalesce.cc @@ -112,9 +112,7 @@ merge_pseudos (int regno1, int regno2) = (lra_merge_live_ranges (lra_reg_info[first].live_ranges, lra_copy_live_range_list (lra_reg_info[first2].live_ranges))); - if (partial_subreg_p (lra_reg_info[first].biggest_mode, - lra_reg_info[first2].biggest_mode)) - lra_reg_info[first].biggest_mode = lra_reg_info[first2].biggest_mode; + lra_update_biggest_mode (first, lra_reg_info[first2].biggest_mode); } /* Change pseudos in *LOC on their coalescing group diff --git a/gcc/lra-int.h b/gcc/lra-int.h index d7ec7c7dc7f..5cdf92be7fc 100644 --- a/gcc/lra-int.h +++ b/gcc/lra-int.h @@ -535,4 +535,19 @@ lra_assign_reg_val (int from, int to) lra_reg_info[to].offset = lra_reg_info[from].offset; } +/* Update REGNO's biggest recorded mode so that it includes a reference + in mode MODE. */ +inline void +lra_update_biggest_mode (int regno, machine_mode mode) +{ + if (!ordered_p (GET_MODE_SIZE (lra_reg_info[regno].biggest_mode), + GET_MODE_SIZE (mode))) + { + gcc_checking_assert (HARD_REGISTER_NUM_P (regno)); + lra_reg_info[regno].biggest_mode = reg_raw_mode[regno]; + } + else if (partial_subreg_p (lra_reg_info[regno].biggest_mode, mode)) + lra_reg_info[regno].biggest_mode = mode; +} + #endif /* GCC_LRA_INT_H */ diff --git a/gcc/lra-lives.cc b/gcc/lra-lives.cc index f60e564da82..0b204232849 100644 --- a/gcc/lra-lives.cc +++ b/gcc/lra-lives.cc @@ -770,9 +770,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) { int regno = reg->regno; - if (partial_subreg_p (lra_reg_info[regno].biggest_mode, - reg->biggest_mode)) - lra_reg_info[regno].biggest_mode = reg->biggest_mode; + lra_update_biggest_mode (regno, reg->biggest_mode); if (HARD_REGISTER_NUM_P (regno)) lra_hard_reg_usage[regno] += freq; } diff --git a/gcc/lra.cc b/gcc/lra.cc index c917a1adee2..29e2a3506e1 100644 --- a/gcc/lra.cc +++ b/gcc/lra.cc @@ -581,9 +581,8 @@ new_insn_reg (rtx_insn *insn, int regno, enum op_type type, lra_insn_reg *ir = lra_insn_reg_pool.allocate (); ir->type = type; ir->biggest_mode = mode; - if (NONDEBUG_INSN_P (insn) - && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode)) - lra_reg_info[regno].biggest_mode = mode; + if (NONDEBUG_INSN_P (insn)) + lra_update_biggest_mode (regno, mode); ir->subreg_p = subreg_p; ir->early_clobber_alts = early_clobber_alts; ir->regno = regno; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr112278.c b/gcc/testsuite/gcc.target/aarch64/sve/pr112278.c new file mode 100644 index 00000000000..4f56add2b0a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr112278.c @@ -0,0 +1,15 @@ +#include +#include + +void +f (void) +{ + { + register svint8_t v0 asm ("z0"); + asm volatile ("" : "=w" (v0)); + } + { + register int8x8x4_t v0 asm ("v0"); + asm volatile ("" : "=w" (v0)); + } +}