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[8.43.85.97]) by mx.google.com with ESMTPS id s6-20020ac85cc6000000b0041961ddd98esi1882003qta.329.2023.10.17.15.49.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 15:49:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C85E3858C2A for ; Tue, 17 Oct 2023 22:49:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 4BC353858C52 for ; Tue, 17 Oct 2023 22:48:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4BC353858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4BC353858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697582937; cv=none; b=MrsaaChpRC2VRy3b4JWf/V1PTFAFkluGEA3tk4WaubuKasSertEj/KMNqQ7enARolkcU8LMSMa1OBGooRL/iz8ivfKRJGRqLsiMjIWco/H6u5ASrax4VXsYRI4DUob6fCMXHJsYGFaOcvwsARF8q5rncSvBe6cDkqVN42QU4AXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697582937; c=relaxed/simple; bh=NF/AL8lE3Yc4T1i4Y6QQE7vB9jKFxRkJ3L3f9rwF/2g=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=L2MIpwekfDyjVuIFypFvbwoZetUHUDlFh7sqz5uDTcViQN1IHAbKB9Jom7aOmHJGDj2dr1UDvXLsAEVaRTCNOUdoCTrDs8K0WdoLFVTAO3Olc5c5B8gRDf2yXg4gOnWQYFTu9vdM8rgwCjgmK9R0ZRy42Jk87PGq4sEpwzHU/OY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1CDD2F4; Tue, 17 Oct 2023 15:49:35 -0700 (PDT) Received: from localhost (unknown [10.32.110.65]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AC883F64C; Tue, 17 Oct 2023 15:48:54 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, jose.marchesi@oracle.com, richard.sandiford@arm.com Cc: jose.marchesi@oracle.com Subject: [PATCH 2/2] aarch64: Put LR save slot first in more cases Date: Tue, 17 Oct 2023 23:48:53 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux) MIME-Version: 1.0 X-Spam-Status: No, score=-24.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780044750322771252 X-GMAIL-MSGID: 1780044750322771252 Now that the prologue and epilogue code iterates over saved registers in offset order, we can put the LR save slot first without compromising LDP/STP formation. This isn't worthwhile when shadow call stacks are enabled, since the first two registers are also push/pop candidates, and LR cannot be popped when shadow call stacks are enabled. (LR is instead loaded first and compared against the shadow stack's value.) But otherwise, it seems better to put the LR save slot first, to reduce unnecessary variation with the layout for stack clash protection. Tested on aarch64-linux-gnu & pushed. Richard gcc/ * config/aarch64/aarch64.cc (aarch64_layout_frame): Don't make the position of the LR save slot dependent on stack clash protection unless shadow call stacks are enabled. gcc/testsuite/ * gcc.target/aarch64/test_frame_2.c: Expect x30 to come before x19. * gcc.target/aarch64/test_frame_4.c: Likewise. * gcc.target/aarch64/test_frame_7.c: Likewise. * gcc.target/aarch64/test_frame_10.c: Likewise. --- gcc/config/aarch64/aarch64.cc | 2 +- gcc/testsuite/gcc.target/aarch64/test_frame_10.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/test_frame_2.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/test_frame_4.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/test_frame_7.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e8b5dfe4d58..62b1ae0652f 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -8694,7 +8694,7 @@ aarch64_layout_frame (void) allocate_gpr_slot (R29_REGNUM); allocate_gpr_slot (R30_REGNUM); } - else if (flag_stack_clash_protection + else if ((flag_stack_clash_protection || !frame.is_scs_enabled) && known_eq (frame.reg_offset[R30_REGNUM], SLOT_REQUIRED)) /* Put the LR save slot first, since it makes a good choice of probe for stack clash purposes. The idea is that the link register usually diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c index c19505082fa..c54ab2d0ccb 100644 --- a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c +++ b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c @@ -14,6 +14,6 @@ t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10]) t_frame_run (test10) -/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, \[0-9\]+\\\]" 1 } } */ -/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp, \[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, \[0-9\]+\\\]" 1 } } */ +/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp, \[0-9\]+\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c index 7e5df84cf5f..0d715314cb8 100644 --- a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c +++ b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c @@ -14,6 +14,6 @@ t_frame_pattern (test2, 200, "x19") t_frame_run (test2) -/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */ -/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, -\[0-9\]+\\\]!" 1 } } */ +/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\], \[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c index ed13487a094..b41229c42f4 100644 --- a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c +++ b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c @@ -13,6 +13,6 @@ t_frame_pattern (test4, 400, "x19") t_frame_run (test4) -/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */ -/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp, -\[0-9\]+\\\]!" 1 } } */ +/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\], \[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c index 96452794956..5702656a5da 100644 --- a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c +++ b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c @@ -13,6 +13,6 @@ t_frame_pattern (test7, 700, "x19") t_frame_run (test7) -/* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp]" 1 } } */ -/* { dg-final { scan-assembler "ldp\tx19, x30, \\\[sp\\\]" } } */ +/* { dg-final { scan-assembler-times "stp\tx30, x19, \\\[sp]" 1 } } */ +/* { dg-final { scan-assembler "ldp\tx30, x19, \\\[sp\\\]" } } */