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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id k18-20020aa7d8d2000000b0043bc450a117si2709898eds.407.2022.07.29.05.15.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jul 2022 05:15:39 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C82C7385AC2C for ; Fri, 29 Jul 2022 12:15:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id 727EE3858424 for ; Fri, 29 Jul 2022 12:15:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 727EE3858424 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.93,201,1654588800"; d="scan'208";a="80376665" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa3.mentor.iphmx.com with ESMTP; 29 Jul 2022 04:14:59 -0800 IronPort-SDR: zPEjQ48ZyP+GimNs5/OJ8EM2f714XsWLRs6ZLyA1nhjtW3s2r2wfdqAD30Pe2Kgc3ktBrAAWtX R69DjJ/R7JZZW+LGcFB5SwH+EKn8GTFKBFU113pgStt+X+biih0IICM2K4loHcNGkwtT028W7r 8VQcv8yYKLe4PJusoJR4MQgeZm9aaUxDAQym7KKjC0Bl5chshuofCMtw60qn5S5Llz4pIKbI/4 LC7/+huj4BS6WjpairV45zd+km36x5K6E+x6WVzT7dYkBVimDsv0BSjTgJp/a0Z/NOZZs+ITa3 hgY= Message-ID: Date: Fri, 29 Jul 2022 13:14:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.0.3 Content-Language: en-GB To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed] amdgcn: 64-bit vector shifts X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-13.mgc.mentorg.com (139.181.222.13) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1739689232960213356?= X-GMAIL-MSGID: =?utf-8?q?1739689232960213356?= I've committed this patch to implement V64DImode vector-vector and vector-scalar shifts. In particular, these are used by the SIMD "inbranch" clones that I'm working on right now, but it's an omission that ought to have been fixed anyway. Andrew amdgcn: 64-bit vector shifts Enable 64-bit vector-vector and vector-scalar shifts. gcc/ChangeLog: * config/gcn/gcn-valu.md (V_INT_noHI): New iterator. (3): Use V_INT_noHI. (v3): Likewise. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index abe46201344..8c33ae0c717 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -60,6 +60,8 @@ (define_mode_iterator V_noHI (define_mode_iterator V_INT_noQI [V64HI V64SI V64DI]) +(define_mode_iterator V_INT_noHI + [V64SI V64DI]) ; All of above (define_mode_iterator V_ALL @@ -2086,10 +2088,10 @@ (define_expand "3" }) (define_insn "3" - [(set (match_operand:V_SI 0 "register_operand" "= v") - (shiftop:V_SI - (match_operand:V_SI 1 "gcn_alu_operand" " v") - (vec_duplicate:V_SI + [(set (match_operand:V_INT_noHI 0 "register_operand" "= v") + (shiftop:V_INT_noHI + (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v") + (vec_duplicate: (match_operand:SI 2 "gcn_alu_operand" "SvB"))))] "" "v_0\t%0, %2, %1" @@ -2117,10 +2119,10 @@ (define_expand "v3" }) (define_insn "v3" - [(set (match_operand:V_SI 0 "register_operand" "=v") - (shiftop:V_SI - (match_operand:V_SI 1 "gcn_alu_operand" " v") - (match_operand:V_SI 2 "gcn_alu_operand" "vB")))] + [(set (match_operand:V_INT_noHI 0 "register_operand" "=v") + (shiftop:V_INT_noHI + (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v") + (match_operand: 2 "gcn_alu_operand" "vB")))] "" "v_0\t%0, %2, %1" [(set_attr "type" "vop2")