diff mbox series

[committed] amdgcn: 64-bit vector shifts

Message ID ffc14703-132a-45a9-97f3-91a7ee419a1c@codesourcery.com
State New, archived
Headers
Series [committed] amdgcn: 64-bit vector shifts |

Commit Message

Andrew Stubbs July 29, 2022, 12:14 p.m. UTC 
  I've committed this patch to implement V64DImode vector-vector and 
vector-scalar shifts.

In particular, these are used by the SIMD "inbranch" clones that I'm 
working on right now, but it's an omission that ought to have been fixed 
anyway.

Andrew
amdgcn: 64-bit vector shifts

Enable 64-bit vector-vector and vector-scalar shifts.

gcc/ChangeLog:

	* config/gcn/gcn-valu.md (V_INT_noHI): New iterator.
	(<expander><mode>3<exec>): Use V_INT_noHI.
	(v<expander><mode>3<exec>): Likewise.
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Patch

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index abe46201344..8c33ae0c717 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -60,6 +60,8 @@  (define_mode_iterator V_noHI
 
 (define_mode_iterator V_INT_noQI
 		      [V64HI V64SI V64DI])
+(define_mode_iterator V_INT_noHI
+		      [V64SI V64DI])
 
 ; All of above
 (define_mode_iterator V_ALL
@@ -2086,10 +2088,10 @@  (define_expand "<expander><mode>3"
   })
 
 (define_insn "<expander><mode>3<exec>"
-  [(set (match_operand:V_SI 0 "register_operand"  "= v")
-	(shiftop:V_SI
-	  (match_operand:V_SI 1 "gcn_alu_operand" "  v")
-	  (vec_duplicate:V_SI
+  [(set (match_operand:V_INT_noHI 0 "register_operand"  "= v")
+	(shiftop:V_INT_noHI
+	  (match_operand:V_INT_noHI 1 "gcn_alu_operand" "  v")
+	  (vec_duplicate:<VnSI>
 	    (match_operand:SI 2 "gcn_alu_operand"  "SvB"))))]
   ""
   "v_<revmnemonic>0\t%0, %2, %1"
@@ -2117,10 +2119,10 @@  (define_expand "v<expander><mode>3"
   })
 
 (define_insn "v<expander><mode>3<exec>"
-  [(set (match_operand:V_SI 0 "register_operand"  "=v")
-	(shiftop:V_SI
-	  (match_operand:V_SI 1 "gcn_alu_operand" " v")
-	  (match_operand:V_SI 2 "gcn_alu_operand" "vB")))]
+  [(set (match_operand:V_INT_noHI 0 "register_operand"  "=v")
+	(shiftop:V_INT_noHI
+	  (match_operand:V_INT_noHI 1 "gcn_alu_operand" " v")
+	  (match_operand:<VnSI> 2 "gcn_alu_operand"	"vB")))]
   ""
   "v_<revmnemonic>0\t%0, %2, %1"
   [(set_attr "type" "vop2")