From patchwork Wed Oct 5 19:08:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 1743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp746667wrs; Wed, 5 Oct 2022 12:11:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7JegM70Fyt6AMgNmz78TCq5lRCdCpHhtYw2zFGgMv3TOqGMj0oJWsYZZzQTwIPVmp5c/th X-Received: by 2002:a17:907:80b:b0:77a:86a1:db52 with SMTP id wv11-20020a170907080b00b0077a86a1db52mr915439ejb.294.1664997084886; Wed, 05 Oct 2022 12:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664997084; cv=none; d=google.com; s=arc-20160816; b=E5pzz0vXifF1KxGsSPSaaQPpGXx46iAR2e5SNjt1KIzfIjVkC9S0y32Lz2FPXL8MoO iI4ZdNIw4JKcTRnC8pS/yBHmyVUGzef+MQzoqpmyHyqnoi3qUJoLIh8B/DVVDdCGXdkV Ljwu2aRA1fSam225M5HNFJkVDO3HOqtCNbsfWvbTF4SkxcTSDDMO4jQQECjmkQ+FYGwy ssISXPglMlLQDhdNwqlQ8HimqXBcLQMs/v63WIBe2SFCwFHuZJQx9uyaXagP1qsDJWCm X29EY0iks4C5JkC8f0D09fdH65itLVcz+UgvvmysN9wRG6SK1ChWXBZYxM/+UTJz3W7k 68Jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :references:in-reply-to:message-id:date:subject:to:from:dmarc-filter :delivered-to; bh=/C0rGB6aJ3P6EM3Qooy702J8+ItwY/bieaTBGTi2dFc=; b=E0x7S8tL1/ZiT+tyO/wDTSB7wWfmGDFR8ocWibraC32nTbF36RQ3TO6jJ2CvOIrUol eFASof32UI2abBpG91Pz2wdl2QF9u+sFKxDxcHDbvQi01239xOywJUkhgNb4pllHC4HY QIcMwi28XSzzoX4wFX/5fELxe/QvaWOmEx+xy0DtJ+u/kUqhJRvoc/Mqy6oRUsf5jo9h sor+QrmMxedg6+AAFUbkD8hXVctRkTIjG22Ef4BNpr01tvDT1cCB+024qSTUpCGrGAlw +knkbQf2cpRFWf74Mw3K6HOvEV0Menrp9PMOCoP08fSbJXiLFK2/WWGbmocc1JRFjzD2 px3A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id o18-20020a509b12000000b004519cd16132si14800854edi.61.2022.10.05.12.11.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 12:11:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D8E213857362 for ; Wed, 5 Oct 2022 19:10:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id 472EB3858023 for ; Wed, 5 Oct 2022 19:09:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 472EB3858023 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id DD46512406DD; Wed, 5 Oct 2022 19:09:00 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] rs6000: Rework vsx_extract_ Date: Wed, 5 Oct 2022 19:08:40 +0000 Message-Id: X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Segher Boessenkool , dje.gcc@gmail.com, "Kewen.Lin" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745875983425545210?= X-GMAIL-MSGID: =?utf-8?q?1745875983425545210?= Extracting the left and right halfs of a vector are entirely different operations. Things are simpler if they are separate define_insns, and it is easy to get rid of the "wD" constraint use then. This also give the variant that is a no-op copy its own alternative, of length 0 (and this, cost 0, making it more likely RA will choose it. 2022-10-05 Segher Boessenkool * config/rs6000/vsx.md (vsx_extract_): Replace define_insn by a define_expand. Split the contents to... (*vsx_extract__0): ... this. Rewrite. (*vsx_extract__01: ... and this. Rewrite. --- gcc/config/rs6000/vsx.md | 80 ++++++++++++++++++++++-------------------------- 1 file changed, 37 insertions(+), 43 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 79a759b1ccf3..e0e34a78bca1 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3388,59 +3388,53 @@ (define_expand "vsx_set_" ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all -(define_insn "vsx_extract_" - [(set (match_operand: 0 "gpc_reg_operand" "=wa, wa, wr, wr") +(define_expand "vsx_extract_" + [(set (match_operand: 0 "gpc_reg_operand") (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") + (match_operand:VSX_D 1 "gpc_reg_operand") (parallel - [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] + [(match_operand:QI 2 "const_0_to_1_operand")])))] "VECTOR_MEM_VSX_P (mode)" + "") + +(define_insn "*vsx_extract__0" + [(set (match_operand: 0 "gpc_reg_operand" "=wa,wa,wr") + (vec_select: + (match_operand:VSX_D 1 "gpc_reg_operand" "0,wa,wa") + (parallel + [(match_operand:QI 2 "const_0_to_1_operand" "n,n,n")])))] + "VECTOR_MEM_VSX_P (mode) + && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 0 : 1)" { - int element = INTVAL (operands[2]); - int op0_regno = REGNO (operands[0]); - int op1_regno = REGNO (operands[1]); - int fldDM; + if (which_alternative == 0) + return ASM_COMMENT_START " vec_extract to same register"; - gcc_assert (IN_RANGE (element, 0, 1)); - gcc_assert (VSX_REGNO_P (op1_regno)); + if (which_alternative == 2) + return "mfvsrd %0,%x1"; - if (element == VECTOR_ELEMENT_SCALAR_64BIT) - { - if (op0_regno == op1_regno) - return ASM_COMMENT_START " vec_extract to same register"; + return "xxlor %x0,%x1,%x1"; +} + [(set_attr "type" "*,veclogical,mfvsr") + (set_attr "isa" "*,*,p8v") + (set_attr "length" "0,*,*")]) - else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE - && TARGET_POWERPC64) - return "mfvsrd %0,%x1"; - - else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno)) - return "fmr %0,%1"; - - else if (VSX_REGNO_P (op0_regno)) - return "xxlor %x0,%x1,%x1"; - - else - gcc_unreachable (); - } - - else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno) - && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE) +(define_insn "*vsx_extract__1" + [(set (match_operand: 0 "gpc_reg_operand" "=wa,wr") + (vec_select: + (match_operand:VSX_D 1 "gpc_reg_operand" "wa,wa") + (parallel + [(match_operand:QI 2 "const_0_to_1_operand" "n,n")])))] + "VECTOR_MEM_VSX_P (mode) + && INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 1 : 0)" +{ + if (which_alternative == 1) return "mfvsrld %0,%x1"; - else if (VSX_REGNO_P (op0_regno)) - { - fldDM = element << 1; - if (!BYTES_BIG_ENDIAN) - fldDM = 3 - fldDM; - operands[3] = GEN_INT (fldDM); - return "xxpermdi %x0,%x1,%x1,%3"; - } - - else - gcc_unreachable (); + operands[3] = GEN_INT (BYTES_BIG_ENDIAN ? 2 : 3); + return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm") - (set_attr "isa" "*,*,p8v,p9v")]) + [(set_attr "type" "mfvsr,vecperm") + (set_attr "isa" "*,p9v")]) ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract___load"