diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h
new file mode 100644
index 00000000000..06376b2da0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-run-template.h
@@ -0,0 +1,47 @@
+#include <stdio.h>
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)					\
+  TYPE a##TYPE[SZ];					\
+  TYPE b##TYPE[SZ];	  				\
+  for (int i = 0; i < SZ; i++)				\
+  {                             			\
+    a##TYPE[i] = VAL;             			\
+    b##TYPE[i] = i % 4;           		       	\
+  }                             			\
+  vshl_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);		\
+  for (int i = 0; i < SZ; i++)				\
+    assert (a##TYPE[i] == (VAL << (i % 4)));
+
+#define RUN2(TYPE,VAL)					\
+  TYPE as##TYPE[SZ];					\
+  TYPE bs##TYPE[SZ];					\
+  for (int i = 0; i < SZ; i++)				\
+  {                             			\
+    as##TYPE[i] = VAL;            			\
+    bs##TYPE[i] = i % 4;				\
+  }                             			\
+  vshiftr_##TYPE (as##TYPE, as##TYPE, bs##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)				\
+    assert (as##TYPE[i] == (VAL >> (i % 4)));
+
+#define RUN_ALL()	\
+ RUN(int16_t, 1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, 3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, 5)	\
+ RUN(uint64_t, 6)       \
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c
new file mode 100644
index 00000000000..ed16bf69355
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv32gcv.c
@@ -0,0 +1,12 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "shift-template.h"
+#include "shift-run-template.h"
+
+/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
+   Therefore, expect only 4 vsll.vv instead of 6 for now.  */
+
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c
new file mode 100644
index 00000000000..5dbfdfbd549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-rv64gcv.c
@@ -0,0 +1,12 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "shift-template.h"
+#include "shift-run-template.h"
+
+/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
+   Therefore, expect only 4 vsll.vv instead of 6 for now.  */
+
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c
new file mode 100644
index 00000000000..bec6ae7130e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "shift-scalar-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c
new file mode 100644
index 00000000000..2c46b12c343
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "shift-scalar-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsll\.vi} 31 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h
new file mode 100644
index 00000000000..a0ddc00849d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-scalar-template.h
@@ -0,0 +1,119 @@
+/* Test shifts by scalar (immediate or register) amount.  */
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */
+
+#include <stdint.h>
+#include <assert.h>
+
+#define SHIFTL(TYPE,VAL)				\
+  __attribute__ ((noipa))                               \
+  void vsll_##TYPE_##VAL (TYPE *dst, int n)		\
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] <<= VAL;					\
+  }
+
+#define SHIFTR(TYPE,VAL)				\
+  __attribute__ ((noipa))                               \
+  void vsrx_##TYPE_##VAL (TYPE *dst, int n)		\
+  {                                                     \
+    for (int i = 0; i < n; i++)                         \
+      dst[i] >>= VAL;					\
+  }
+
+#define TEST_ALL()	\
+SHIFTL(uint32_t,1)    	\
+SHIFTL(uint32_t,2)    	\
+SHIFTL(uint32_t,3)    	\
+SHIFTL(uint32_t,4)      \
+SHIFTL(uint32_t,5)      \
+SHIFTL(uint32_t,6)      \
+SHIFTL(uint32_t,7)	\
+SHIFTL(uint32_t,8)	\
+SHIFTL(uint32_t,9)	\
+SHIFTL(uint32_t,10)	\
+SHIFTL(uint32_t,11)	\
+SHIFTL(uint32_t,12)	\
+SHIFTL(uint32_t,13)	\
+SHIFTL(uint32_t,14)	\
+SHIFTL(uint32_t,15)	\
+SHIFTL(uint32_t,16)	\
+SHIFTL(uint32_t,17)	\
+SHIFTL(uint32_t,18)	\
+SHIFTL(uint32_t,19)	\
+SHIFTL(uint32_t,20)	\
+SHIFTL(uint32_t,21)	\
+SHIFTL(uint32_t,22)	\
+SHIFTL(uint32_t,23)	\
+SHIFTL(uint32_t,24)	\
+SHIFTL(uint32_t,25)	\
+SHIFTL(uint32_t,26)	\
+SHIFTL(uint32_t,27)	\
+SHIFTL(uint32_t,28)	\
+SHIFTL(uint32_t,29)	\
+SHIFTL(uint32_t,30)	\
+SHIFTL(uint64_t,31)	\
+
+TEST_ALL()
+
+#define SZ 32
+
+#define TEST_VSLL(TYPE,VAL)		\
+  TYPE a##TYPE##VAL[SZ];	  	\
+  for (int i = 0; i < SZ; i++)		\
+    a##TYPE##VAL[i] = 2;		\
+  vsll_##TYPE_##VAL (a##TYPE##VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)	  	\
+    assert (a##TYPE##VAL[i] == (2ll << VAL));
+
+__attribute__((noipa))
+void vsllvx (uint32_t *dst, int val, int n)
+{
+  for (int i = 0; i < n; i++)
+    dst[i] <<= val;
+}
+
+#define TEST_VSLLVX		\
+  uint32_t a[SZ];	  	\
+  for (int i = 0; i < SZ; i++)		\
+    a[i] = 2;		\
+  vsllvx (a, 17, SZ);	\
+  for (int i = 0; i < SZ; i++)	  	\
+    assert (a[i] == (2 << 17));
+
+int main ()
+{
+  TEST_VSLL(uint32_t,1)
+  TEST_VSLL(uint32_t,2)
+  TEST_VSLL(uint32_t,3)
+  TEST_VSLL(uint32_t,4)
+  TEST_VSLL(uint32_t,5)
+  TEST_VSLL(uint32_t,6)
+  TEST_VSLL(uint32_t,7)
+  TEST_VSLL(uint32_t,8)
+  TEST_VSLL(uint32_t,9)
+  TEST_VSLL(uint32_t,10)
+  TEST_VSLL(uint32_t,11)
+  TEST_VSLL(uint32_t,12)
+  TEST_VSLL(uint32_t,13)
+  TEST_VSLL(uint32_t,14)
+  TEST_VSLL(uint32_t,15)
+  TEST_VSLL(uint32_t,16)
+  TEST_VSLL(uint32_t,17)
+  TEST_VSLL(uint32_t,18)
+  TEST_VSLL(uint32_t,19)
+  TEST_VSLL(uint32_t,20)
+  TEST_VSLL(uint32_t,21)
+  TEST_VSLL(uint32_t,22)
+  TEST_VSLL(uint32_t,23)
+  TEST_VSLL(uint32_t,24)
+  TEST_VSLL(uint32_t,25)
+  TEST_VSLL(uint32_t,26)
+  TEST_VSLL(uint32_t,27)
+  TEST_VSLL(uint32_t,28)
+  TEST_VSLL(uint32_t,29)
+  TEST_VSLL(uint32_t,30)
+  TEST_VSLL(uint64_t,31)
+
+  TEST_VSLLVX
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h
new file mode 100644
index 00000000000..64e0a386b06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/shift-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST1_TYPE(TYPE)					\
+  __attribute__((noipa))					\
+  void vshl_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)		\
+  {								\
+    for (int i = 0; i < n; i++)					\
+      dst[i] = a[i] << b[i];					\
+  }
+
+#define TEST2_TYPE(TYPE)					\
+  __attribute__((noipa))					\
+  void vshiftr_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {								\
+    for (int i = 0; i < n; i++)					\
+      dst[i] = a[i] >> b[i];					\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST1_TYPE(int16_t)	\
+ TEST1_TYPE(uint16_t)	\
+ TEST1_TYPE(int32_t)	\
+ TEST1_TYPE(uint32_t)	\
+ TEST1_TYPE(int64_t)	\
+ TEST1_TYPE(uint64_t)   \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h
new file mode 100644
index 00000000000..498cf780d91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-run-template.h
@@ -0,0 +1,64 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;            		\
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == VAL);
+
+#define RUN3(TYPE,VAL)				\
+  TYPE ai##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    ai##TYPE[i] = VAL;				\
+  vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (ai##TYPE[i] == VAL + 15);
+
+#define RUN3M(TYPE,VAL)				\
+  TYPE aim##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    aim##TYPE[i] = VAL;				\
+  vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (aim##TYPE[i] == VAL - 16);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)    \
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)   \
+ RUN3M(int16_t, 13)	\
+ RUN3(uint16_t, 14)	\
+ RUN3M(int32_t, 15)	\
+ RUN3(uint32_t, 16)	\
+ RUN3M(int64_t, 17)	\
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c
new file mode 100644
index 00000000000..8c5fe43fc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vadd-template.h"
+#include "vadd-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c
new file mode 100644
index 00000000000..a821be9361f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vadd-template.h"
+#include "vadd-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h
new file mode 100644
index 00000000000..5ed79329138
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vadd-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] + b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] + b;				\
+  }
+
+#define TEST3_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vaddi_##TYPE (TYPE *dst, TYPE *a, int n)	        \
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] + 15;				\
+  }
+
+#define TEST3M_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vaddim_##TYPE (TYPE *dst, TYPE *a, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] - 16;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)	\
+ TEST3_TYPE(uint16_t)	\
+ TEST3M_TYPE(int32_t)	\
+ TEST3_TYPE(uint32_t)	\
+ TEST3M_TYPE(int64_t)	\
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h
new file mode 100644
index 00000000000..f9e40ef5aae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-run-template.h
@@ -0,0 +1,64 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 123;				\
+    b##TYPE[i] = VAL;				\
+  }                             		\
+  vand_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == (TYPE)(123 & VAL));
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 123;				\
+  vands_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == (123 & VAL));
+
+#define RUN3(TYPE,VAL)				\
+  TYPE ai##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    ai##TYPE[i] = VAL;				\
+  vandi_##TYPE (ai##TYPE, ai##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (ai##TYPE[i] == (VAL & 15));
+
+#define RUN3M(TYPE,VAL)				\
+  TYPE aim##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    aim##TYPE[i] = VAL;				\
+  vandim_##TYPE (aim##TYPE, aim##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (aim##TYPE[i] == (VAL & -16));
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)	\
+ RUN3M(int16_t, 13)	\
+ RUN3(uint16_t, 14)	\
+ RUN3M(int32_t, 15)	\
+ RUN3(uint32_t, 16)	\
+ RUN3M(int64_t, 17)	\
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c
new file mode 100644
index 00000000000..5745732a94a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vand-template.h"
+#include "vand-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c
new file mode 100644
index 00000000000..4ac3e50b24a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vand-template.h"
+#include "vand-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h
new file mode 100644
index 00000000000..7d02c83d164
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vand-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] & b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vands_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] & b;				\
+  }
+
+#define TEST3_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vandi_##TYPE (TYPE *dst, TYPE *a, int n)	        \
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] & 15;				\
+  }
+
+#define TEST3M_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vandim_##TYPE (TYPE *dst, TYPE *a, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] & -16;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)	\
+ TEST3_TYPE(uint16_t)	\
+ TEST3M_TYPE(int32_t)	\
+ TEST3_TYPE(uint32_t)	\
+ TEST3M_TYPE(int64_t)	\
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h
new file mode 100644
index 00000000000..92539d4a294
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = VAL * 3;       		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 3);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = VAL * 5;			\
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 5);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c
new file mode 100644
index 00000000000..9015f4be732
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vdiv-template.h"
+#include "vdiv-run-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vdiv.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c
new file mode 100644
index 00000000000..ca32890f99b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vdiv-template.h"
+#include "vdiv-run-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vdiv.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h
new file mode 100644
index 00000000000..7fbba7b4133
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vdiv-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] / b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] / b;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h
new file mode 100644
index 00000000000..fd01240b240
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vmax_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;				\
+  vmaxs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c
new file mode 100644
index 00000000000..7b26aaa8808
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmax-template.h"
+#include "vmax-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c
new file mode 100644
index 00000000000..82baeabf9e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmax-template.h"
+#include "vmax-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h
new file mode 100644
index 00000000000..df0f9f2aeeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmax-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] > b[i] ? a[i] : b[i];		\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vmaxs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] > b ? a[i] : b;			\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h
new file mode 100644
index 00000000000..078353b3ec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vmin_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;				\
+  vmins_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)    \
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c
new file mode 100644
index 00000000000..e02d4bb8656
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmin-template.h"
+#include "vmin-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c
new file mode 100644
index 00000000000..9be9204122b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmin-template.h"
+#include "vmin-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h
new file mode 100644
index 00000000000..459f58ddec1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmin-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] < b[i] ? a[i] : b[i];		\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vmins_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] < b ? a[i] : b;			\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h
new file mode 100644
index 00000000000..3f671a39b4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 2;				\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 2 * VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 3;            		\
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 3 * VAL);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c
new file mode 100644
index 00000000000..0e3bd6e0f0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmul-template.h"
+#include "vmul-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c
new file mode 100644
index 00000000000..4a304e3312d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vmul-template.h"
+#include "vmul-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h
new file mode 100644
index 00000000000..b029c06efd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmul-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] * b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] * b;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h
new file mode 100644
index 00000000000..fed7f141b78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-run-template.h
@@ -0,0 +1,64 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 123;           		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)	  	\
+    assert (a##TYPE[i] == (123 | VAL));
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 123;          		\
+  vors_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == (123 | VAL));
+
+#define RUN3(TYPE,VAL)				\
+  TYPE ai##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    ai##TYPE[i] = VAL;				\
+  vori_##TYPE (ai##TYPE, ai##TYPE, SZ);		\
+  for (int i = 0; i < SZ; i++)	  		\
+    assert (ai##TYPE[i] == (VAL | 15));
+
+#define RUN3M(TYPE,VAL)				\
+  TYPE aim##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    aim##TYPE[i] = VAL;				\
+  vorim_##TYPE (aim##TYPE, aim##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (aim##TYPE[i] == (VAL | -16));
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)	\
+ RUN3M(int16_t, 13)	\
+ RUN3(uint16_t, 14)	\
+ RUN3M(int32_t, 15)	\
+ RUN3(uint32_t, 16)	\
+ RUN3M(int64_t, 17)	\
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c
new file mode 100644
index 00000000000..434f00821eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vor-template.h"
+#include "vor-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c
new file mode 100644
index 00000000000..a821be9361f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vadd-template.h"
+#include "vadd-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h
new file mode 100644
index 00000000000..859ae67c5ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vor-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] | b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] | b;				\
+  }
+
+#define TEST3_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vori_##TYPE (TYPE *dst, TYPE *a, int n)	        \
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] | 15;				\
+  }
+
+#define TEST3M_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vorim_##TYPE (TYPE *dst, TYPE *a, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] | -16;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)	\
+ TEST3_TYPE(uint16_t)	\
+ TEST3M_TYPE(int32_t)	\
+ TEST3_TYPE(uint32_t)	\
+ TEST3M_TYPE(int64_t)	\
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h
new file mode 100644
index 00000000000..0dd8ed6c07f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];	  			\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 37;				\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vrem_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 37 % VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 89;           		\
+  vrems_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 89 % VAL);
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c
new file mode 100644
index 00000000000..bbb6b94db85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vrem-template.h"
+#include "vrem-run-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vrem.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c
new file mode 100644
index 00000000000..f98155b095d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c
@@ -0,0 +1,10 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vrem-template.h"
+#include "vrem-run-template.h"
+
+/* TODO: Implement vector type promotion.  We should have 6 vrem.vv here.  */
+
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h
new file mode 100644
index 00000000000..71eebc8b645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vrem-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vrem_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] % b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vrems_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] % b;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h
new file mode 100644
index 00000000000..cf9454b6bbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-run-template.h
@@ -0,0 +1,42 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 999;           		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 999 - VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 999;            		\
+  vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 999 - VAL);
+
+#define RUN_ALL()	\
+ RUN(int16_t, 1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, 3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, 5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, 7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, 9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, 11)	\
+ RUN2(uint64_t, 12)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c
new file mode 100644
index 00000000000..cebb40fb791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vsub-template.h"
+#include "vsub-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c
new file mode 100644
index 00000000000..cef6b712654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c
@@ -0,0 +1,7 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vsub-template.h"
+#include "vsub-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h
new file mode 100644
index 00000000000..0566f3dcbfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vsub-template.h
@@ -0,0 +1,34 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsub_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] - b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsubs_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] - b;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h
new file mode 100644
index 00000000000..c10357a22f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-run-template.h
@@ -0,0 +1,64 @@
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 123;           		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vxor_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == (123 ^ VAL));
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 123;          		\
+  vxors_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == (123 ^ VAL));
+
+#define RUN3(TYPE,VAL)				\
+  TYPE ai##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    ai##TYPE[i] = VAL;				\
+  vxori_##TYPE (ai##TYPE, ai##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (ai##TYPE[i] == (VAL ^ 15));
+
+#define RUN3M(TYPE,VAL)				\
+  TYPE aim##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    aim##TYPE[i] = VAL;				\
+  vxorim_##TYPE (aim##TYPE, aim##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (aim##TYPE[i] == (VAL ^ -16));
+
+#define RUN_ALL()	\
+ RUN(int16_t, -1)	\
+ RUN(uint16_t, 2)	\
+ RUN(int32_t, -3)	\
+ RUN(uint32_t, 4)	\
+ RUN(int64_t, -5)	\
+ RUN(uint64_t, 6)	\
+ RUN2(int16_t, -7)	\
+ RUN2(uint16_t, 8)	\
+ RUN2(int32_t, -9)	\
+ RUN2(uint32_t, 10)	\
+ RUN2(int64_t, -11)	\
+ RUN2(uint64_t, 12)	\
+ RUN3M(int16_t, 13)	\
+ RUN3(uint16_t, 14)	\
+ RUN3M(int32_t, 15)	\
+ RUN3(uint32_t, 16)	\
+ RUN3M(int64_t, 17)	\
+ RUN3(uint64_t, 18)
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c
new file mode 100644
index 00000000000..e32b9b0e661
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vxor-template.h"
+#include "vxor-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c
new file mode 100644
index 00000000000..70839bf822e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -save-temps" } */
+
+#include "vxor-template.h"
+#include "vxor-run-template.h"
+
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h
new file mode 100644
index 00000000000..954a247f539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vxor-template.h
@@ -0,0 +1,56 @@
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] ^ b[i];				\
+  }
+
+#define TEST2_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vxors_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] ^ b;				\
+  }
+
+#define TEST3_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vxori_##TYPE (TYPE *dst, TYPE *a, int n)	        \
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] ^ 15;				\
+  }
+
+#define TEST3M_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vxorim_##TYPE (TYPE *dst, TYPE *a, int n)	\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = a[i] ^ -16;				\
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()	\
+ TEST_TYPE(int16_t)	\
+ TEST_TYPE(uint16_t)	\
+ TEST_TYPE(int32_t)	\
+ TEST_TYPE(uint32_t)	\
+ TEST_TYPE(int64_t)	\
+ TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int16_t)	\
+ TEST2_TYPE(uint16_t)	\
+ TEST2_TYPE(int32_t)	\
+ TEST2_TYPE(uint32_t)	\
+ TEST2_TYPE(int64_t)	\
+ TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int16_t)	\
+ TEST3_TYPE(uint16_t)	\
+ TEST3M_TYPE(int32_t)	\
+ TEST3_TYPE(uint32_t)	\
+ TEST3M_TYPE(int64_t)	\
+ TEST3_TYPE(uint64_t)
+
+TEST_ALL()
