From patchwork Thu Nov 2 13:34:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 160881 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp357447vqu; Thu, 2 Nov 2023 06:34:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHlySdqvHrF18zDCDJS1Y7cUsGOGx2XP2NddsBUlJhNExra4qX9gYnMx0n8gj+1ubA7qP3G X-Received: by 2002:a05:620a:1a26:b0:76f:1817:942b with SMTP id bk38-20020a05620a1a2600b0076f1817942bmr20704436qkb.28.1698932092342; Thu, 02 Nov 2023 06:34:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698932092; cv=pass; d=google.com; s=arc-20160816; b=yoUCb+I0pW2eLdW797GhXUJT7zxJsVephiSjqzz9pmIJ+WnBN8qpV53cmD56w497SL pWiuS/NPTqyGuSLsCICPeqSs9lmu0orttjTGIE6nonriLfgaY3MzRTWJfdB6266h6TLv Tu656jmmzFC17jQALF+RfaUYr9qwDYrtNswEUEeWaLA/ew1td3o/3v4KWCdgigfRB1+U ChKa03/nb4oc4tytiwroHaMCc5IFMlTA8OlvI9Cdyki25LmJkAGzr7bPdXYVA5PsZ8MW pD4t/DbGhSYCkR3TREzV3vu2HOV6FS3HuIiwIrpgxPi/bQ5rDKrPFdJ95ddXrukxsA6m 2NXw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:to:subject:from :content-language:user-agent:mime-version:date:message-id :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=61RZfG5ev+cpxjGnejQwo6/fOnkmBz5H7vuMnijVtCQ=; fh=XNn3asQvIblazGK92GBt13dVv+YmGV3pBS0JC29ZQco=; b=fcdW1Fxbvi8Ji2G65OVGOKwIGq4Ojcjzta1pCvPdPEdxb0elgLGT2P7jw32x8wzMXy GgHhxLx0w970H9sBuPsyeLrY8jjWU3IYLN0fJwvVfwdEKHCg4Z2plKjmft/1th/ostr7 TQPFqLuEy+Zl+lo42n3uFnbZ8HZxOLj6FmarvHQkiQhc8TZ9rFE8thD9p5dD42drgMBZ bkQHY1tN31BB1tAV3ynnDsrrkoNPERLRim5IVQWd48N+wTNqpIniweZy3PrAjowPhSLL WJbK3k29mPNmezBCMwQ9slPwbj8P3z0BWVBshcLL9YCBJlyEZhGAqOUfnrgbptBeYE3h 0IJA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=i6vlU7CO; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l28-20020a05620a211c00b007741ee6ce02si4456958qkl.104.2023.11.02.06.34.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 06:34:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=i6vlU7CO; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DA8283858421 for ; Thu, 2 Nov 2023 13:34:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 274AB3858C41 for ; Thu, 2 Nov 2023 13:34:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 274AB3858C41 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 274AB3858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::62f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698932067; cv=none; b=P+SvvvcYvhZM68d4wdF9Zj80YUXwV5S8deEZoYruc9r1W/2lJLBGI6oxyNYRwdlxEKR/AvqUCialVkQYJCL+0RfEzyiMLS+boxQkklVCINMI1ww2vBMorbknAfGS9Sme3Qg27isYCZuh1PwU5oHodgU3z00vkzX08KbmrA+S2gU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698932067; c=relaxed/simple; bh=Dxn6aZAdGZ/9r/dPsmU2b3PaCMgZyp/7+45X+k3cJf0=; h=DKIM-Signature:Message-ID:Date:MIME-Version:From:Subject:To; b=Psh6CEnSqyzsgzKxESij5A+aC1qvMpJ+DlCT81/7MbTpqBpuZsp9rpGsniJtOQMMyE5O6Gy4XbdvU15xHd80F1UwjJSqtoD7cQQg2G8RMiWUJYB9yAvo0On8rdDoWCfCTTJ2WZuwAw2nbO+CVHhupAaDelJCMSWU0rF4J8EdRRI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc2fc281cdso7600315ad.0 for ; Thu, 02 Nov 2023 06:34:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1698932055; x=1699536855; darn=gcc.gnu.org; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=61RZfG5ev+cpxjGnejQwo6/fOnkmBz5H7vuMnijVtCQ=; b=i6vlU7CO4rKll6lVQLcRb0XF1JtemV7RrgBEnscOA+nK/wOqpVLEfKve20md01SsFf EtZ19kQX+ZL6XMZQTYBUGNgWthpXrPhVI6KqQggCj0/Wv1pdmDQj/EHjVI9lyY5rGBtC owFx2GLyhoRXHiuz85Mn5NsbwTHoT7JehLAJrsV5M41tjEjJplRDp7ZKpYLUg2MzW3jJ 3pA9ON/6zvc+KO64jP9CF8H1dtVA25k8DBg1dcUtTvJLhS1bQV3o/9I/qYDv1Iec+Bro onXWgsX6Q7QDzSXpOOgmywL+2nzHjTC5H8E35SRBLVFv0u5u8dbbEZdOzdjjw4X94jVO HRMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698932055; x=1699536855; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=61RZfG5ev+cpxjGnejQwo6/fOnkmBz5H7vuMnijVtCQ=; b=ph77xYIt4R/o8hyeI2vObFktxz926McV4X6Otl16VaZLVBc/UkNagtVbnzMMs2Ff/p nD4SEuFpgLV+fwzjssti6ypNe/BhIHHBvBhVhDZRDo66e1hh7sALkLWa3MeA6vm/TSYA E8Kw3elQO0VGwUSPseWUGSZTzlFyVE828lhSRzkdZEXx9xXA36xxvfBMjmrQUD+xjzuJ 2+WAMOc50uQse5+uzY494eDLb4l+yhcZ9b2SzhJPI/LoKSQS9VPUgXDhbvVvTdBt4T40 LZd6w1PnunNqsOAtwOxFXFC8LnGx5ufipJQI9qvDCQoAuJqIlRCVnHVQKd1IpLelJCzD RvYA== X-Gm-Message-State: AOJu0YyffDjoZ3hqao0hlzTAIbyCNx4Sjn5SkmJoPi3ftec5burHL31X u+y8+GaPxSXHQC/L0heY7IZADOUrXJs= X-Received: by 2002:a17:902:c78c:b0:1c9:d8b6:e7ad with SMTP id w12-20020a170902c78c00b001c9d8b6e7admr14601716pla.56.1698932055055; Thu, 02 Nov 2023 06:34:15 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id d8-20020a170902cec800b001b81a97860asm3103668plg.27.2023.11.02.06.34.13 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Nov 2023 06:34:14 -0700 (PDT) Message-ID: Date: Thu, 2 Nov 2023 07:34:13 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Jeff Law Subject: [committed] Improve H8 sequences for single bit sign extractions To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781459417298275405 X-GMAIL-MSGID: 1781459417298275405 Spurred by Roger's recent work on ARC, this patch improves the code we generation for single bit sign extractions. The basic idea is to get the bit we want into C, the use a subx;ext.w;ext.l sequence to sign extend it in a GPR. For bits 0..15 we can use a bld instruction to get the bit we want into C. For bits 16..31, we can move the high word into the low word, then use bld. There's a couple special cases where we can shift the bit we want from the high word into C which is an instruction smaller. Not surprisingly most cases seen in newlib and the test suite are extractions from the low byte, HImode sign bit and top two bits of SImode. Regression tested on the H8 with no regressions. Installing on the trunk. Jeff commit 0f9f3fc885a1f830ff09a095e8c14919c2796a9d Author: Jeff Law Date: Thu Nov 2 07:25:39 2023 -0600 [committed] Improve H8 sequences for single bit sign extractions Spurred by Roger's recent work on ARC, this patch improves the code we generation for single bit sign extractions. The basic idea is to get the bit we want into C, the use a subx;ext.w;ext.l sequence to sign extend it in a GPR. For bits 0..15 we can use a bld instruction to get the bit we want into C. For bits 16..31, we can move the high word into the low word, then use bld. There's a couple special cases where we can shift the bit we want from the high word into C which is an instruction smaller. Not surprisingly most cases seen in newlib and the test suite are extractions from the low byte, HImode sign bit and top two bits of SImode. Regression tested on the H8 with no regressions. Installing on the trunk. gcc/ * config/h8300/combiner.md: Add new patterns for single bit sign extractions. diff --git a/gcc/config/h8300/combiner.md b/gcc/config/h8300/combiner.md index fd5cf2f4af4..2f7faf77c93 100644 --- a/gcc/config/h8300/combiner.md +++ b/gcc/config/h8300/combiner.md @@ -1268,3 +1268,94 @@ (define_insn "" ;; (label_ref (match_dup 1)) ;; (pc)))] ;; "") + +;; Various ways to extract a single bit bitfield and sign extend it +;; +;; Testing showed this only triggering with SImode, probably because +;; of how insv/extv are defined. +(define_insn_and_split "" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extract:SI (match_operand:QHSI 1 "register_operand" "0") + (const_int 1) + (match_operand 2 "immediate_operand")))] + "" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (sign_extract:SI (match_dup 1) (const_int 1) (match_dup 2))) + (clobber (reg:CC CC_REG))])]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extract:SI (match_operand:QHSI 1 "register_operand" "0") + (const_int 1) + (match_operand 2 "immediate_operand"))) + (clobber (reg:CC CC_REG))] + "" +{ + int position = INTVAL (operands[2]); + + /* For bit position 31, 30, left shift the bit we want into C. */ + bool bit_in_c = false; + if (position == 31) + { + output_asm_insn ("shll.l\t%0", operands); + bit_in_c = true; + } + else if (position == 30 && TARGET_H8300S) + { + output_asm_insn ("shll.l\t#2,%0", operands); + bit_in_c = true; + } + + /* Similar for positions 16, 17, but with a right shift into C. */ + else if (position == 16) + { + output_asm_insn ("shlr.w\t%e0", operands); + bit_in_c = true; + } + else if (position == 17 && TARGET_H8300S) + { + output_asm_insn ("shlr.w\t#2,%e0", operands); + bit_in_c = true; + } + + + /* For all the other cases in the upper 16 bits, move the upper 16 + bits into the lower 16 bits, then use the standard sequence for + extracting one of the low 16 bits. */ + else if (position >= 16) + { + output_asm_insn ("mov.w\t%e1,%f0", operands); + + /* We'll use the standard sequences for the low word now. */ + position %= 16; + } + + /* Same size/speed as the general sequence, but slightly faster + to simulate. */ + if (position == 0) + return "and.l\t#1,%0\;neg.l\t%0"; + + rtx xoperands[3]; + xoperands[0] = operands[0]; + xoperands[1] = operands[1]; + xoperands[2] = GEN_INT (position); + + /* If the bit we want is not already in C, get it there */ + if (!bit_in_c) + { + if (position >= 8) + { + xoperands[2] = GEN_INT (position % 8); + output_asm_insn ("bld\t%2,%t1", xoperands); + } + else + output_asm_insn ("bld\t%2,%s1", xoperands); + } + + /* Now the bit we want is in C, emit the generalized sequence + to get that bit into the destination, properly extended. */ + return "subx\t%s0,%s0\;exts.w %T0\;exts.l %0"; +} + [(set_attr "length" "10")])