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[8.43.85.97]) by mx.google.com with ESMTPS id ks30-20020a056214311e00b0066d0a6ee60asi5267202qvb.226.2023.10.23.00.25.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 00:25:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@irq.a4lg.com header.s=2017s01 header.b=rWEIOCZj; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=irq.a4lg.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B92093853508 for ; Mon, 23 Oct 2023 07:25:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id A3E6F3861918 for ; Mon, 23 Oct 2023 07:24:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A3E6F3861918 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A3E6F3861918 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2401:2500:203:30b:4000:6bfe:4757:0 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045876; cv=none; b=pG8GQEb1x6NZ+IsRy8y04u2PIA0lEKORBJfKk7OawSUla2PimbdQb1HBofS1Xj9lC1rhc8n+QTMNtDH6yzY3ZoPRbU6TmwSYBWQxkQhfgA3hl+a8kvBYLybIPQVNP6nO26bJ/NGpIk28eh5WErCWaYKt/8gFCV1eDamQENkFMg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698045876; c=relaxed/simple; bh=XZVf9qy/8MX4/4GW09e02M0gVhNIo/qJAPoiUXWhoP0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=BmGUPCAAsoqp7n8x51+gqnyluXPxhskMZr7XOwm2gOzNFqObwXzgmvibOkeaKfMRkSh4f4lef+WmfJtnFgOmsuyz5grXvzv39PFY5QG7uwKfJUiEg1SrF4P0OedXQ7O9hvUQz6nQasN/INrmP5NO+uQCFGb1rC8MK/VEQCg4KG4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 92791300089; Mon, 23 Oct 2023 07:24:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045872; bh=wXpO+y3EjFiyaydSnnRbwAJYTwxX7PmnveCKXJbYPU0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=rWEIOCZj60d4ZIN96TVGkt2F3gBHMvXZGUYPQp+0BCtDuz9xp6Mz8K9r2cJRU5Pmo WPEpiqucVD7hfy4nexUMw/bHnqbBUnMxhnNEqHYSyWR2XnknK5pHKSq/najg2u8eVV +iBEn595QGUeshPV+GWxwOUC0ezU8wTIG/v+ehTo= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion Date: Mon, 23 Oct 2023 07:22:55 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780530192115243890 X-GMAIL-MSGID: 1780530192115243890 From: Tsukasa OI A "prefetch" instruction on RISC-V GCC emits a machine hint instruction directly when the 'Zicbop' extension is enabled but it could cause an ICE when the address argument of __builtin_prefetch is an integral constant (such like 0 [NULL] or some other [but possibly not all] fixed addresses). This is caused by the fact that the "r" constraint is not actually checked and something other than a register can be the first argument of the "prefetch" RTL instruction. It fixes the problem by changing "prefetch" from a native instruction to an expansion and coercing the address to a register there. gcc/ChangeLog: * config/riscv/riscv.md (prefetch): Expand to a native prefetch instruction instead of emitting a machine instruction directly. Coerce the address argument into a register. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbop-by-common-ice-1.c: New ICE test. * gcc.target/riscv/cmo-zicbop-by-common-ice-2.c: Ditto. --- gcc/config/riscv/riscv.md | 43 ++++++++++++------- .../riscv/cmo-zicbop-by-common-ice-1.c | 13 ++++++ .../riscv/cmo-zicbop-by-common-ice-2.c | 7 +++ 3 files changed, 48 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e67a6d1f1b81..bf232345b1ab 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3479,21 +3479,6 @@ [(set_attr "type" "cbo")] ) -(define_insn "prefetch" - [(prefetch (match_operand 0 "address_operand" "r") - (match_operand 1 "imm5_operand" "i") - (match_operand 2 "const_int_operand" "n"))] - "TARGET_ZICBOP" -{ - switch (INTVAL (operands[1])) - { - case 0: return "prefetch.r\t%a0"; - case 1: return "prefetch.w\t%a0"; - default: gcc_unreachable (); - } -} - [(set_attr "type" "cbo")]) - (define_insn "riscv_prefetch_r_" [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_PREFETCH_R)] @@ -3508,6 +3493,34 @@ "prefetch.w\t0(%0)" [(set_attr "type" "cbo")]) +(define_expand "prefetch" + [(prefetch (match_operand 0 "address_operand" "") + (match_operand 1 "const_int_operand" "") + (match_operand 2 "const_int_operand" ""))] + "TARGET_ZICBOP" +{ + operands[0] = force_reg (Pmode, operands[0]); + switch (INTVAL (operands[1])) + { + case 0: + if (TARGET_64BIT) + emit_insn (gen_riscv_prefetch_r_di (operands[0])); + else + emit_insn (gen_riscv_prefetch_r_si (operands[0])); + break; + case 1: + if (TARGET_64BIT) + emit_insn (gen_riscv_prefetch_w_di (operands[0])); + else + emit_insn (gen_riscv_prefetch_w_si (operands[0])); + break; + default: + gcc_unreachable (); + } + DONE; +} + [(set_attr "type" "cbo")]) + (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c new file mode 100644 index 000000000000..47e83f29cc5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zicbop -mabi=ilp32" } */ + +void foo (void) +{ + /* Second argument defaults to zero (read). */ + __builtin_prefetch (0); + __builtin_prefetch (0, 0); + __builtin_prefetch (0, 1); +} + +/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */ +/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c new file mode 100644 index 000000000000..a245b8163c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zicbop -mabi=lp64" } */ + +#include "cmo-zicbop-by-common-ice-1.c" + +/* { dg-final { scan-assembler-times "prefetch\\.r" 2 } } */ +/* { dg-final { scan-assembler-times "prefetch\\.w" 1 } } */