diff mbox series

[v3,2/3] RISC-V: Add stub support for existing extensions (vendor)

Message ID e8e8da2e7c301dc17870b98c2684be1ace3a847a.1693280368.git.research_trasio@irq.a4lg.com
State Unresolved
Headers
Series RISC-V: Add stub support for existing extensions |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Tsukasa OI Aug. 29, 2023, 3:39 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects or programs
with inline assembler, GCC should support almost all extensions that
Binutils support, even if the GCC itself does not touch a thing.

This commit adds stub supported vendor extensions to
riscv_ext_version_table (no riscv_implied_info entries to add; all
information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
	Add stub support for all vendor extensions supported by Binutils.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-30.c: New test for a stub
	vendor extension 'XVentanaCondOps'.
---
 gcc/common/config/riscv/riscv-common.cc    |  2 ++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 ++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c

Comments

Jeff Law Aug. 29, 2023, 1:42 p.m. UTC | #1 
On 8/28/23 21:39, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
> extensions") changed how do we handle unknown extensions, we have no
> guarantee that we can share the same architectural string with Binutils
> (specifically, the assembler).
> 
> To avoid compilation errors on shared Assembler-C/C++ projects or programs
> with inline assembler, GCC should support almost all extensions that
> Binutils support, even if the GCC itself does not touch a thing.
> 
> This commit adds stub supported vendor extensions to
> riscv_ext_version_table (no riscv_implied_info entries to add; all
> information is copied from Binutils' bfd/elfxx-riscv.c).
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
> 	Add stub support for all vendor extensions supported by Binutils.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/predef-30.c: New test for a stub
> 	vendor extension 'XVentanaCondOps'.
OK.
jeff
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 3502993026d6..8e2b3ba6d621 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -322,6 +322,8 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
diff --git a/gcc/testsuite/gcc.target/riscv/predef-30.c b/gcc/testsuite/gcc.target/riscv/predef-30.c
new file mode 100644
index 000000000000..9784b9ce5033
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-30.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_xventanacondops -mabi=lp64 -mcmodel=medlow -misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_xventanacondops)
+#error "__riscv_xventanacondops"
+#endif
+
+  return 0;
+}