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server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4614D300089; Mon, 23 Oct 2023 07:24:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1698045840; bh=Ou+C/f0nUEjEAmwvrJe5pRB/WhfOhGmJkEf+zoVJ51M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=f7f3Qi2fk4kGExUuZ+IYx4ElGADJL12v5kReCrGrccpgadHw8d+PuRhDB74IF/6Yd Xs2yhSBOX37kOxNy+z11lj3AAM88wIzwe/6gHPnM/ssERouj2tlkAvF61/yn1XYW9Z 2FIswLXgdxqEfUxxQOT5jS/qyfhNxdqYfKwoX5nQ= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities Date: Mon, 23 Oct 2023 07:22:52 +0000 Message-ID: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780530149886387032 X-GMAIL-MSGID: 1780530149886387032 From: Tsukasa OI Because they are for all prefetch instructions, "prefetch" fits better than "prefetchi". gcc/ChangeLog: * config/riscv/riscv-builtins.cc: Rename availabilities "prefetchi{32,64}" to "prefetch{32,64}". * config/riscv/riscv-cmo.def (__builtin_riscv_zicbop_cbo_prefetchi): Reflect availability name changes. --- gcc/config/riscv/riscv-builtins.cc | 4 ++-- gcc/config/riscv/riscv-cmo.def | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index fc3976f3ba12..ce549eb3782d 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -103,8 +103,8 @@ AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT) AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT) AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) -AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) -AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) +AVAIL (prefetch32, TARGET_ZICBOP && !TARGET_64BIT) +AVAIL (prefetch64, TARGET_ZICBOP && TARGET_64BIT) AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT) AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT) AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def index ff713b78e19e..017370d1d0e3 100644 --- a/gcc/config/riscv/riscv-cmo.def +++ b/gcc/config/riscv/riscv-cmo.def @@ -13,8 +13,8 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64), // zicbop -RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetchi32), -RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetchi64), +RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetch32), +RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetch64), // zbkc or zbc RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),