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[8.43.85.97]) by mx.google.com with ESMTPS id n25-20020a05620a223900b0077891c3f481si3460717qkh.780.2023.10.21.20.50.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 20:50:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@irq.a4lg.com header.s=2017s01 header.b=UG4HVB08; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=irq.a4lg.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 37ACF3858C27 for ; Sun, 22 Oct 2023 03:50:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 44A0F3858D37 for ; Sun, 22 Oct 2023 03:49:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 44A0F3858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 44A0F3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2401:2500:203:30b:4000:6bfe:4757:0 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697946581; cv=none; b=WhC4alT0dDXprv10p63S/5gzHsX+sZhcY75flMqLAdmU264Gqf4r/yeU8hlx0yad88YkmhNYIVmxLsz8oqgaNoXHUxH1ci6rywJDIHb9KbbU2v/gVnQV33BgD6QTIuTIR/VY/t1VReb8pRAoojTsW3yILE3IMppLL213gsSslGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697946581; c=relaxed/simple; bh=F3rS9ygxv9mQQ8+hD+zPvn2pjr7yYDmGZTCtPSyuwUo=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:Mime-Version; b=VZj/zBvi/jV47ocDJnWCPyEVE8fKldavjvuZ9Ovrsd8fmLOW/5DTcIUmm1Wit2R1p+JAdPgBCu9JMF0z4XaGzSsdgT0AvG08KKOUB5bBWVGkeZStGgjHsiXdRNilBZDAF2D/GNIfQ82uOZ5+Xsax3L7BvE8eWbi6Ndn9oNt8vjQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id CFB1E300089; Sun, 22 Oct 2023 03:49:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1697946575; bh=KjLJgO9ppkrxaODesBvH4pTiBluQ3T+4ogHIv4ccq8Q=; h=From:To:Cc:Subject:Date:Message-ID:Mime-Version: Content-Transfer-Encoding; b=UG4HVB089pG1cw1rdqlz/ioyQp+XA7te7LmEiojfSaPyxQuHWAhw/CAm5wpYyebWi pjtNGfA9J6pOTarN2zHRCaz3+SSmGs3JiLp7zjTQ7Bg1I49jnEf2fiB33+9aeKW1tq 6zvTiQYCDYA+AZpeX15VZqTE7QBPAIdSrWhX5kvM= From: Tsukasa OI To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [RFC PATCH] RISC-V: Initial RV64E and LP64E support Date: Sun, 22 Oct 2023 03:49:22 +0000 Message-ID: Mime-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780426058477684065 X-GMAIL-MSGID: 1780426058477684065 From: Tsukasa OI Along with RV32E, RV64E is ratified. Though ILP32E and LP64E ABIs are still draft, it's worth supporting it. This commit should not be merged until two proposals below are going to proceed. LP64E proposal (including suggested changes): New "__riscv_64e" proposal by the author of this commit: gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_std_ext): Allow RV64E. * config.gcc: Parse base ISA RV64E and ABI LP64E. * config/riscv/arch-canonicalize: Parse base ISA 'rv64e'. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Build different macro per RV32E/RV64E. Add handling for ABI_LP64E. * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi): Add handling for ABI_LP64E. * config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E. * config/riscv/riscv.cc (riscv_option_override): Enhance error handling to support RV64E and LP64E. (riscv_conditional_register_usage): Change "RV32E" in a comment to "RV32E/RV64E". * config/riscv/riscv.h (UNITS_PER_FP_ARG): Add handling for ABI_LP64E. (STACK_BOUNDARY): Ditto. (ABI_STACK_BOUNDARY): Ditto. (MAX_ARGS_IN_REGISTERS): Ditto. (ABI_SPEC): Add support for "lp64e". * config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E. * doc/invoke.texi: Add documentation of the LP64E ABI. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-1.c: Test for __riscv_64e. * gcc.target/riscv/predef-2.c: Ditto. * gcc.target/riscv/predef-3.c: Ditto. * gcc.target/riscv/predef-4.c: Ditto. * gcc.target/riscv/predef-5.c: Ditto. * gcc.target/riscv/predef-6.c: Ditto. * gcc.target/riscv/predef-7.c: Ditto. * gcc.target/riscv/predef-8.c: Ditto. * gcc.target/riscv/predef-9.c: New test for RV32E and LP64E, based on predef-7.c. --- gcc/common/config/riscv/riscv-common.cc | 2 +- gcc/config.gcc | 10 ++-- gcc/config/riscv/arch-canonicalize | 2 +- gcc/config/riscv/riscv-c.cc | 3 +- gcc/config/riscv/riscv-d.cc | 1 + gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 19 ++++--- gcc/config/riscv/riscv.h | 17 ++++-- gcc/config/riscv/riscv.opt | 3 ++ gcc/doc/invoke.texi | 7 +-- gcc/testsuite/gcc.target/riscv/predef-1.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-2.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-3.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-4.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-5.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-6.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-7.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-8.c | 3 ++ gcc/testsuite/gcc.target/riscv/predef-9.c | 66 +++++++++++++++++++++++ 19 files changed, 134 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/predef-9.c base-commit: 11f50716eee812c4a27b66f894e7f3ed0c870534 diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 526dbb7603be..14e0bcfc6b5e 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -963,7 +963,7 @@ riscv_subset_list::parse_std_ext (const char *p) add ("e", major_version, minor_version, explicit_version_p, false); - if (m_xlen > 32) + if (m_xlen > 64) { error_at (m_loc, "%<-march=%s%>: rv%de is not a valid base ISA", m_arch, m_xlen); diff --git a/gcc/config.gcc b/gcc/config.gcc index 0782cbc6e915..0f568654ad64 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4684,7 +4684,7 @@ case "${target}" in # Infer arch from --with-arch, --target, and --with-abi. case "${with_arch}" in - rv32e* | rv32i* | rv32g* | rv64i* | rv64g*) + rv32e* | rv32i* | rv32g* | rv64e* | rv64i* | rv64g*) # OK. ;; "") @@ -4693,11 +4693,12 @@ case "${target}" in ilp32e) with_arch="rv32e" ;; ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;; lp64 | lp64f | lp64d) with_arch="rv64gc" ;; + lp64e) with_arch="rv64e" ;; *) with_arch="rv${xlen}gc" ;; esac ;; *) - echo "--with-arch=${with_arch} is not supported. The argument must begin with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2 + echo "--with-arch=${with_arch} is not supported. The argument must begin with rv32e, rv32i, rv32g, rv64e, rv64i, or rv64g." 1>&2 exit 1 ;; esac @@ -4711,7 +4712,7 @@ case "${target}" in # pick a default based on the ISA, preferring soft-float # unless the D extension is present. case "${with_abi}" in - ilp32 | ilp32e | ilp32f | ilp32d | lp64 | lp64f | lp64d) + ilp32 | ilp32e | ilp32f | ilp32d | lp64 | lp64e | lp64f | lp64d) ;; "") case "${with_arch}" in @@ -4719,6 +4720,7 @@ case "${target}" in rv32e*) with_abi=ilp32e ;; rv32*) with_abi=ilp32 ;; rv64*d* | rv64g*) with_abi=lp64d ;; + rv64e*) with_abi=lp64e ;; rv64*) with_abi=lp64 ;; esac ;; @@ -4734,7 +4736,7 @@ case "${target}" in ilp32,rv32* | ilp32e,rv32e* \ | ilp32f,rv32*f* | ilp32f,rv32g* \ | ilp32d,rv32*d* | ilp32d,rv32g* \ - | lp64,rv64* \ + | lp64,rv64* | lp64e,rv64e* \ | lp64f,rv64*f* | lp64f,rv64g* \ | lp64d,rv64*d* | lp64d,rv64g*) ;; diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index bbb9261bd87e..ea2f67a09445 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -83,7 +83,7 @@ def arch_canonicalize(arch, isa_spec): new_arch = "" extra_long_ext = [] std_exts = [] - if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64i', 'rv64g']: + if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64e', 'rv64i', 'rv64g']: new_arch = arch[:5].replace("g", "i") if arch[:5] in ['rv32g', 'rv64g']: std_exts = ['m', 'a', 'f', 'd'] diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 283052ae3131..e84b76e9973a 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -51,7 +51,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__riscv_compressed"); if (TARGET_RVE) - builtin_define ("__riscv_32e"); + builtin_define (TARGET_64BIT ? "__riscv_64e" : "__riscv_32e"); if (TARGET_ATOMIC) builtin_define ("__riscv_atomic"); @@ -76,6 +76,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) switch (riscv_abi) { case ABI_ILP32E: + case ABI_LP64E: builtin_define ("__riscv_abi_rve"); gcc_fallthrough (); diff --git a/gcc/config/riscv/riscv-d.cc b/gcc/config/riscv/riscv-d.cc index cfeafa819784..3ba34708e765 100644 --- a/gcc/config/riscv/riscv-d.cc +++ b/gcc/config/riscv/riscv-d.cc @@ -52,6 +52,7 @@ riscv_d_handle_target_float_abi (void) { case ABI_ILP32E: case ABI_ILP32: + case ABI_LP64E: case ABI_LP64: abi = "soft"; break; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index e557f70f414b..c990a734840c 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -27,6 +27,7 @@ enum riscv_abi_type { ABI_ILP32F, ABI_ILP32D, ABI_LP64, + ABI_LP64E, ABI_LP64F, ABI_LP64D }; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f2dcb0db6fbd..e92e0fc60fed 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8136,13 +8136,18 @@ riscv_option_override (void) error ("requested ABI requires %<-march%> to subsume the %qc extension", UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F')); - if (TARGET_RVE && riscv_abi != ABI_ILP32E) - error ("rv32e requires ilp32e ABI"); + /* RVE requires specific ABI. */ + if (TARGET_RVE) + if (!TARGET_64BIT && riscv_abi != ABI_ILP32E) + error ("rv32e requires ilp32e ABI"); + else if (TARGET_64BIT && riscv_abi != ABI_LP64E) + error ("rv64e requires lp64e ABI"); - // Zfinx require abi ilp32,ilp32e or lp64. - if (TARGET_ZFINX && riscv_abi != ABI_ILP32 - && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) - error ("z*inx requires ABI ilp32, ilp32e or lp64"); + /* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */ + if (TARGET_ZFINX + && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 + && riscv_abi != ABI_ILP32E && riscv_abi != ABI_LP64E) + error ("z*inx requires ABI ilp32, ilp32e, lp64 or lp64e"); /* We do not yet support ILP32 on RV64. */ if (BITS_PER_WORD != POINTER_SIZE) @@ -8235,7 +8240,7 @@ riscv_option_override (void) static void riscv_conditional_register_usage (void) { - /* We have only x0~x15 on RV32E. */ + /* We have only x0~x15 on RV32E/RV64E. */ if (TARGET_RVE) { for (int r = 16; r <= 31; r++) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 01645141935f..5fdeec735bc4 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -168,7 +168,7 @@ ASM_MISA_SPEC /* The largest type that can be passed in floating-point registers. */ #define UNITS_PER_FP_ARG \ ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E \ - || riscv_abi == ABI_LP64) \ + || riscv_abi == ABI_LP64 || riscv_abi == ABI_LP64E) \ ? 0 \ : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8)) @@ -191,10 +191,15 @@ ASM_MISA_SPEC /* The smallest supported stack boundary the calling convention supports. */ #define STACK_BOUNDARY \ - (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD) + (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ + ? BITS_PER_WORD \ + : 2 * BITS_PER_WORD) /* The ABI stack alignment. */ -#define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128) +#define ABI_STACK_BOUNDARY \ + (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ + ? BITS_PER_WORD \ + : 128) /* There is no point aligning anything to a rounder boundary than this. */ #define BIGGEST_ALIGNMENT 128 @@ -665,7 +670,10 @@ enum reg_class #define GP_RETURN GP_ARG_FIRST #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST) -#define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8) +#define MAX_ARGS_IN_REGISTERS \ + (riscv_abi == ABI_ILP32E || riscv_abi == ABI_LP64E \ + ? 6 \ + : 8) #define MAX_ARGS_IN_VECTOR_REGISTERS (16) #define MAX_ARGS_IN_MASK_REGISTERS (1) @@ -1130,6 +1138,7 @@ extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); "%{mabi=ilp32f:ilp32f}" \ "%{mabi=ilp32d:ilp32d}" \ "%{mabi=lp64:lp64}" \ + "%{mabi=lp64e:lp64e}" \ "%{mabi=lp64f:lp64f}" \ "%{mabi=lp64d:lp64d}" \ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 70d78151cee6..71877c993b59 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -64,6 +64,9 @@ Enum(abi_type) String(ilp32d) Value(ABI_ILP32D) EnumValue Enum(abi_type) String(lp64) Value(ABI_LP64) +EnumValue +Enum(abi_type) String(lp64e) Value(ABI_LP64E) + EnumValue Enum(abi_type) String(lp64f) Value(ABI_LP64F) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index aebe9195ef0f..0455874027f5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -29445,9 +29445,10 @@ conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64}, @samp{lp64f}, and @samp{lp64d}. Some calling conventions are impossible to implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is invalid because the ABI requires 64-bit values be passed in F registers, but F -registers are only 32 bits wide. There is also the @samp{ilp32e} ABI that can -only be used with the @samp{rv32e} architecture. This ABI is not well -specified at present, and is subject to change. +registers are only 32 bits wide. There are also the @samp{ilp32e} ABI that can +only be used with the @samp{rv32e} architecture and @samp{lp64e} ABI that can +only be used with the @samp{rv64e}. Those ABI are not well specified at +present, and is subject to change. @opindex mfdiv @item -mfdiv diff --git a/gcc/testsuite/gcc.target/riscv/predef-1.c b/gcc/testsuite/gcc.target/riscv/predef-1.c index 9dddc1849635..250812a10400 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-1.c +++ b/gcc/testsuite/gcc.target/riscv/predef-1.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-2.c b/gcc/testsuite/gcc.target/riscv/predef-2.c index 755fe4ef7d8a..fa5bdea7f3a4 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-2.c +++ b/gcc/testsuite/gcc.target/riscv/predef-2.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if !defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-3.c b/gcc/testsuite/gcc.target/riscv/predef-3.c index 513645351c09..868b56118470 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-3.c +++ b/gcc/testsuite/gcc.target/riscv/predef-3.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if !defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-4.c b/gcc/testsuite/gcc.target/riscv/predef-4.c index 76b6feec6b6f..ba8b5c785a91 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-4.c +++ b/gcc/testsuite/gcc.target/riscv/predef-4.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if !defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-5.c b/gcc/testsuite/gcc.target/riscv/predef-5.c index 54a51508afbd..560d6ea823f1 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-5.c +++ b/gcc/testsuite/gcc.target/riscv/predef-5.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-6.c b/gcc/testsuite/gcc.target/riscv/predef-6.c index f61709f7bf32..8987b72a5db9 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-6.c +++ b/gcc/testsuite/gcc.target/riscv/predef-6.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if !defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-7.c b/gcc/testsuite/gcc.target/riscv/predef-7.c index 41217554c4db..833e2be887dd 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-7.c +++ b/gcc/testsuite/gcc.target/riscv/predef-7.c @@ -13,6 +13,9 @@ int main () { #if !defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-8.c b/gcc/testsuite/gcc.target/riscv/predef-8.c index 982056a53438..8fa8b42f3341 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-8.c +++ b/gcc/testsuite/gcc.target/riscv/predef-8.c @@ -13,6 +13,9 @@ int main () { #if defined(__riscv_32e) #error "__riscv_32e" #endif +#if defined(__riscv_64e) +#error "__riscv_64e" +#endif #if defined(__riscv_atomic) #error "__riscv_atomic" diff --git a/gcc/testsuite/gcc.target/riscv/predef-9.c b/gcc/testsuite/gcc.target/riscv/predef-9.c new file mode 100644 index 000000000000..cc3abc9a741a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-9.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64em -mabi=lp64e -mno-div -mcmodel=medlow" } */ + +int main () { +#if !defined(__riscv) +#error "__riscv" +#endif + +#if defined(__riscv_compressed) +#error "__riscv_compressed" +#endif + +#if defined(__riscv_32e) +#error "__riscv_32e" +#endif +#if !defined(__riscv_64e) +#error "__riscv_64e" +#endif + +#if defined(__riscv_atomic) +#error "__riscv_atomic" +#endif + +#if !defined(__riscv_mul) +#error "__riscv_mul" +#endif +#if defined(__riscv_div) +#error "__riscv_div" +#endif +#if defined(__riscv_muldiv) +#error "__riscv_muldiv" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if defined(__riscv_fdiv) +#error "__riscv_fdiv" +#endif +#if defined(__riscv_fsqrt) +#error "__riscv_fsqrt" +#endif + +#if !defined(__riscv_abi_rve) +#error "__riscv_abi_rve" +#endif +#if !defined(__riscv_float_abi_soft) +#error "__riscv_float_abi_soft" +#endif +#if defined(__riscv_float_abi_single) +#error "__riscv_float_abi_single" +#endif +#if defined(__riscv_float_abi_double) +#error "__riscv_float_abi_double" +#endif + +#if !defined(__riscv_cmodel_medlow) +#error "__riscv_cmodel_medlow" +#endif +#if defined(__riscv_cmodel_medany) +#error "__riscv_cmodel_medlow" +#endif + + return 0; +}