diff mbox series

RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

Message ID e0f91d40-dea8-e398-9678-6ede777de4f0@gmail.com
State Unresolved
Headers
Series RISC-V: testsuite: Add vector_hw and zvfh_hw checks. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Robin Dapp June 14, 2023, 2:06 p.m. UTC 
  Hi,

this introduces new checks for run tests.  Currently we have
riscv_vector as well as rv32 and rv64 which all check if GCC (with the
current configuration) can build (not execute) the respective tests.

Many tests specify e.g. a different -march for vector, though.  So the
check fails even though we could build as well as run the tests (i.e.
when qemu and binfmt are set up properly).

The new vector_hw now tries to compile, link and execute a simple
vector example.  If this succeeds the respective test can run.

Similarly we introduce a zvfh_hw check which will be used in the
upcoming floating-point unop/binop tests as well as rv32_hw and
rv64_hw checks that are currently unused.

I have requested feedback from some of you individually already and
would kindly ask for feedback if this works for folks (or already does
without doing anything?).
With my current gcc configuration (e.g. --target=riscv64-unknown-linux-gnu
--with-sysroot) the riscv_vector check fails and consequently
no vector test is run (UNSUPPORTED).  With the new riscv_vector_hw
check everythings runs on my machine.

Regards
 Robin

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use
	riscv_vector_hw.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/series_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1-run.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c:
	Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito.
	* lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw
	and zvfh_hw checks.
---
 .../riscv/rvv/autovec/binop/shift-run.c       |  2 +-
 .../rvv/autovec/binop/shift-scalar-run.c      |  2 +-
 .../riscv/rvv/autovec/binop/vadd-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vand-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vmax-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vmin-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vmul-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vor-run.c         |  2 +-
 .../riscv/rvv/autovec/binop/vrem-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vsub-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vxor-run.c        |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-1.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-2.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-3.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-4.c       |  2 +-
 .../rvv/autovec/conversions/vfcvt_rtz-run.c   |  2 +-
 .../riscv/rvv/autovec/conversions/vncvt-run.c |  2 +-
 .../riscv/rvv/autovec/conversions/vsext-run.c |  2 +-
 .../riscv/rvv/autovec/conversions/vzext-run.c |  2 +-
 .../autovec/partial/multiple_rgroup_run-1.c   |  2 +-
 .../autovec/partial/multiple_rgroup_run-2.c   |  2 +-
 .../autovec/partial/multiple_rgroup_run-3.c   |  2 +-
 .../autovec/partial/multiple_rgroup_run-4.c   |  2 +-
 .../rvv/autovec/partial/single_rgroup_run-1.c |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-1.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-2.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-3.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-4.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-5.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-6.c     |  2 +-
 .../riscv/rvv/autovec/partial/slp_run-7.c     |  2 +-
 .../riscv/rvv/autovec/series_run-1.c          |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-1.c   |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-2.c   |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-3.c   |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-5.c   |  2 +-
 .../riscv/rvv/autovec/ternop/ternop_run-6.c   |  2 +-
 .../riscv/rvv/autovec/unop/abs-run.c          |  2 +-
 .../riscv/rvv/autovec/unop/vneg-run.c         |  2 +-
 .../riscv/rvv/autovec/unop/vnot-run.c         |  2 +-
 .../autovec/vls-vlmax/full-vec-move1-run.c    |  2 +-
 .../rvv/autovec/vls-vlmax/full-vec-move1.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-1.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-2.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-3.c    |  2 +-
 .../rvv/autovec/vls-vlmax/insert_run-1.c      |  2 +-
 .../rvv/autovec/vls-vlmax/insert_run-2.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c  |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-1.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-2.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-3.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-4.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-5.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-6.c      |  2 +-
 .../riscv/rvv/autovec/vmv-imm-run.c           |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-1.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-2.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-3.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-4.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-5.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-6.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-7.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-8.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-9.c     |  2 +-
 gcc/testsuite/lib/target-supports.exp         | 84 +++++++++++++++++++
 73 files changed, 156 insertions(+), 72 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index d7052b2270c..56361f6c2c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "shift-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
index a8ecf9767e5..e4eb57ac99a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "shift-scalar-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 4f6c8e773c3..65f61b0e932 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vadd-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index 3fa6cf35e18..0854561ab6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vand-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index c4fd81f4bf2..810757a8834 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vdiv-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index 668f848694b..d889f28b298 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vmax-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index 63c05a119a9..a5887e6097f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vmin-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index ca0dc9130e4..e7de703bfaf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vmul-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index f6b3770dcbb..30ba27a7b2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index 58b69ec393e..a797862366b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vrem-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index f024eb0c04b..3d0b937cf3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vsub-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index 7239733d12c..ffbad73c74f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vxor-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
index a84d22d2a73..e0786abce65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "vcond-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
index 56fd39f4691..e3e4707c987 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 /* { dg-require-effective-target fenv_exceptions } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
index e50d561bd98..50e6eb23278 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */
 /* { dg-require-effective-target fenv_exceptions } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
index 6c45c274c33..2492312554d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "vcond-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
index 05f8d911ad7..6865076ac87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
 
 #include "vfcvt_rtz-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
index f55d2dfce7f..1b9311c15fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vncvt-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
index d5f0190957a..1bcd50196ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vsext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
index 9d1c259f592..85373ced39c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vzext-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
index d3e187eae68..7520bc483e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
 
 #include "multiple_rgroup-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
index 5166c9e35a0..8531849b9c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
 
 #include "multiple_rgroup-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
index b786738ce99..44840042950 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
 
 #include "multiple_rgroup-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
index 7751384183e..720c0f562ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
 
 #include "multiple_rgroup-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
index 4af2f18de8a..440d76403ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */
 
 #include "single_rgroup-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
index 16f078a0433..5a2569a4123 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
index 41f688f628c..27a984513fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
index 30996cb2c6e..86247e5b53c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
index 3d43ef0890c..8fa7aa335e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
index 814308bd7af..61a3cc9af03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
index e317eeac2f2..74b0df31ac4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
index a8e4781988e..f5afd17c184 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
 
 #include "slp-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
index 09a20809c65..d50558b4751 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */
 
 #include "series-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
index 1f69b694818..976de18cff4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
index 103b98acdf0..98433e06abd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
index eac5408ce6f..1ad4492453e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
index c6f1fe591f3..79ba4dd3f60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
index 81af4b672a5..8f82f86760e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
index b5e579ef55a..4b7c6b93ce4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include "ternop-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index d864b54229b..d93a7c768d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "abs-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
index abeb50f21ea..98c7f30ec56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vneg-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
index 2870b21a218..a7f44db41ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vnot-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1-run.c
index fa01881cd16..09a183aa741 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b" } */
 
 #include "full-vec-move1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index 55888d5ff07..b6b204196a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b" } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
index f7c2fdd040d..d6752e99310 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "init-repeat-sequence-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
index 5564dd4a05a..078fe813f08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "init-repeat-sequence-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
index fec5adc56de..f993125d5ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "init-repeat-sequence-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
index 7eb129cde68..a195df342af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "insert-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
index e3b97be385b..efa6541d306 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "insert-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index cb216a9543c..78a8f5fd959 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index 1b51b315ad1..27a4aa01d0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 4cae7f4f1a5..46aa2006163 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index e60b19fab68..19dfddd1ecd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index b61990915b0..bb8bceffe85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index b23df90f0ac..e5444253ffb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "perm-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index d935d36bf69..7b8c6824621 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */
 
 #include "perm-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
index 85ec963c47b..a3d0df579d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "repeat-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
index cb054b6c43c..e786bd533e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "repeat-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
index 2cbe1c2bf95..ba0b7609caf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 #include "repeat-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
index 9efb6b2bc39..93e7d40b8af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "repeat-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
index efd7d293c0b..a2d1fd99359 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "repeat-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
index 53836956c3b..d50c21b1f3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
 
 #include "repeat-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
index faa6c907337..9c7a3f64bca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */
 
 #include "vmv-imm-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
index 6cdeb571711..fcca23e8115 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
index 84baa515610..fa09d38dafc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
index beb0cc2b58b..86185d57908 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
index a14539f72ae..55157b1cce1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
index ca16585a945..5ed28101d66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
index 5b69c2ab0c6..5757255f0ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
index 4abddd5d718..56d744152f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
index f4840d30dc2..5d85aea9d85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
index 2caa09a2c5a..f323897a05a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
@@ -1,4 +1,4 @@ 
-/* { dg-do run { target { riscv_vector } } } */
+/* { dg-do run { target { riscv_vector_hw } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
 
 #include <assert.h>
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 184fafb020f..87b5a4459e2 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1804,9 +1804,35 @@  proc check_effective_target_riscv_vector { } {
     }]
 }
 
+# Return 1 if the target can execute RISC-V vector instructions, 0 otherwise.
+
+proc check_effective_target_riscv_vector_hw { } {
+    return {[check_runtime riscv_check_vector_hw {
+	int main (void)
+	{
+	    asm ("vsetivli zero,8,e16,m1,ta,ma");
+	    asm ("vadd.vv v8,v8,v16" : : : "v8");
+	    return 0;
+	}
+    } "-march=rv64gcv -mabi=lp64d" ]
+    ||
+    [check_runtime riscv_check_vector_hw {
+	int main (void)
+	{
+	    asm ("vsetivli zero,8,e16,m1,ta,ma");
+	    asm ("vadd.vv v8,v8,v16" : : : "v8");
+	    return 0;
+	}
+    } "-march=rv32gcv -mabi=ilp32d" ]}
+}
+
 # Return 1 if the target is RV32, 0 otherwise.  Cache the result.
 
 proc check_effective_target_rv32 { } {
+    if { ![istarget rv32*-*-*] } then {
+	return 0
+    }
+
     # Check that we are compiling for RV32 by checking the xlen size.
     return [check_no_compiler_messages riscv_rv32 assembly {
        #if !defined(__riscv_xlen)
@@ -1819,9 +1845,26 @@  proc check_effective_target_rv32 { } {
     }]
 }
 
+# Return 1 if the target can execute RV32 executables, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_rv32_hw { } {
+    return [check_runtime riscv_check_rv32_hw {
+	int main (void)
+	{
+	    asm ("add t0,t1,t2");
+	    return 0;
+	}
+    } "-march=rv32gc -mabi=ilp32d"]
+}
+
 # Return 1 if the target is RV64, 0 otherwise.  Cache the result.
 
 proc check_effective_target_rv64 { } {
+    if { ![istarget rv64*-*-*] } then {
+	return 0
+    }
+
     # Check that we are compiling for RV64 by checking the xlen size.
     return [check_no_compiler_messages riscv_rv64 assembly {
        #if !defined(__riscv_xlen)
@@ -1834,6 +1877,47 @@  proc check_effective_target_rv64 { } {
     }]
 }
 
+# Return 1 if the target can execute RV64 executables, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_rv64_hw { } {
+    return [check_runtime riscv_check_rv64_hw {
+	int main (void)
+	{
+	    asm ("addiw t1,t2,4095");
+	    return 0;
+	}
+    } "-march=rv64gc -mabi=lp64d"]
+}
+
+# Return 1 if the target supports the zvfh extension and can execute it,
+# 0 otherwise. Cache the result.
+
+proc check_effective_target_riscv_zvfh_hw { } {
+    if ![check_effective_target_riscv_vector_hw] then {
+	return 0
+    }
+
+    return [
+	{[check_runtime riscv_check_zvfh_hw {
+	    int main (void)
+	    {
+		asm ("vsetivli zero,8,e16,m1,ta,ma");
+		asm ("vfadd.vv v8,v8,v16" : : : "v8");
+		return 0;
+	    }
+	} "-march=rv64gcv_zvfh -mabi=lp64d"]
+	||
+	[check_runtime riscv_check_zvfh {
+	    int main (void)
+	    {
+		asm ("vsetivli zero,8,e16,m1,ta,ma");
+		asm ("vfadd.vv v8,v8,v16" : : : "v8");
+		return 0;
+	    }
+	} "-march=rv32gcv_zvfh -mabi=ilp32d"]}
+}
+
 # Return 1 if the target OS supports running SSE executables, 0
 # otherwise.  Cache the result.