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Mon, 8 Jan 2024 02:35:50 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 84F4320040; Mon, 8 Jan 2024 02:35:48 +0000 (GMT) Received: from [9.197.233.114] (unknown [9.197.233.114]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 8 Jan 2024 02:35:48 +0000 (GMT) Message-ID: Date: Mon, 8 Jan 2024 10:35:46 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Content-Language: en-US To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner From: "Kewen.Lin" Subject: [PATCH] rs6000: Eliminate zext fed by vclzlsbb [PR111480] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5j4Ff0ry7ck7Z_MulaEl0fC4V6t9gZVh X-Proofpoint-ORIG-GUID: 05fP_Ukkx0nYgWd_fgFR4h-4W3If6fBd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-07_15,2024-01-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=766 suspectscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 mlxscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401080017 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787488038349424304 X-GMAIL-MSGID: 1787488038349424304 Hi, As PR111480 shows, commit r14-4079 only optimizes the case of vctzlsbb but not for the similar vclzlsbb. This patch is to consider vclzlsbb as well and avoid the failure on the reported test case. It also simplifies the patterns with iterator and attribute. Bootstrapped and regtested on powerpc64-linux-gnu P8/P9 and powerpc64le-linux-gnu P9 and P10. I'm going to push this soon. BR, Kewen ----- PR target/111480 gcc/ChangeLog: * config/rs6000/vsx.md (VCZLSBB): New int iterator. (vczlsbb_char): New int attribute. (vclzlsbb_, vctzlsbb_): Merge to ... (vczlsbb_): ... this. (*vctzlsbb_zext_): Rename to ... (*vczlsbb_zext_): ... this, and extend it to cover vclzlsbb. --- gcc/config/rs6000/vsx.md | 41 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 23 deletions(-) -- 2.42.0 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 4c1725a7ecd..6111cc90eb7 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -411,6 +411,12 @@ (define_mode_attr VM3_char [(V2DI "d") (V2DF "d") (V4SF "w")]) +;; Iterator and attribute for vector count leading/trailing +;; zero least-significant bits byte +(define_int_iterator VCZLSBB [UNSPEC_VCLZLSBB + UNSPEC_VCTZLSBB]) +(define_int_attr vczlsbb_char [(UNSPEC_VCLZLSBB "l") + (UNSPEC_VCTZLSBB "t")]) ;; VSX moves @@ -5855,35 +5861,24 @@ (define_insn "vcmpnezw" "vcmpnezw %0,%1,%2" [(set_attr "type" "vecsimple")]) -;; Vector Count Leading Zero Least-Significant Bits Byte -(define_insn "vclzlsbb_" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI - [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")] - UNSPEC_VCLZLSBB))] - "TARGET_P9_VECTOR" - "vclzlsbb %0,%1" - [(set_attr "type" "vecsimple")]) - -;; Vector Count Trailing Zero Least-Significant Bits Byte -(define_insn "*vctzlsbb_zext_" +;; Vector Count Leading/Trailing Zero Least-Significant Bits Byte +(define_insn "*vczlsbb_zext_" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (unspec:SI - [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")] - UNSPEC_VCTZLSBB)))] + (zero_extend:DI + (unspec:SI + [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")] + VCZLSBB)))] "TARGET_P9_VECTOR" - "vctzlsbb %0,%1" + "vczlsbb %0,%1" [(set_attr "type" "vecsimple")]) -;; Vector Count Trailing Zero Least-Significant Bits Byte -(define_insn "vctzlsbb_" +(define_insn "vczlsbb_" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI - [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")] - UNSPEC_VCTZLSBB))] + (unspec:SI + [(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v")] + VCZLSBB))] "TARGET_P9_VECTOR" - "vctzlsbb %0,%1" + "vczlsbb %0,%1" [(set_attr "type" "vecsimple")]) ;; Vector Extract Unsigned Byte Left-Indexed