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Wed, 27 Sep 2023 05:38:13 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C3E142004D; Wed, 27 Sep 2023 05:38:13 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9B7FB20063; Wed, 27 Sep 2023 05:38:11 +0000 (GMT) Received: from [9.177.71.47] (unknown [9.177.71.47]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 27 Sep 2023 05:38:11 +0000 (GMT) Message-ID: Date: Wed, 27 Sep 2023 13:38:09 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Content-Language: en-US From: "Kewen.Lin" Subject: [PATCH] rs6000: Make 32 bit stack_protect support prefixed insn [PR111367] To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner , Michael Meissner X-TM-AS-GCONF: 00 X-Proofpoint-GUID: XVypRBx37MbsJs2P7w6kf9gVjhaZblqy X-Proofpoint-ORIG-GUID: r9D1SbeLetUM908YQR1B4Rsg6uEcuu7_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-27_02,2023-09-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309270045 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778168022089962374 X-GMAIL-MSGID: 1778168022089962374 Hi, As PR111367 shows, with prefixed insn supported, some of checkings consider it's able to leverage prefixed insn for stack protect related load/store, but since we don't actually change the emitted assembly for 32 bit, it can cause the assembler error as exposed. Mike's commit r10-4547-gce6a6c007e5a98 has already handled the 64 bit case (DImode), this patch is to treat the 32 bit case (SImode) by making use of mode iterator P and ptrload attribute iterator, also fixes the constraints to match the emitted operand formats. Bootstrapped and regtested on powerpc64-linux-gnu P7/P8/P9 and powerpc64le-linux-gnu P9. This patch has incorporated Segher's comments in PR111367, I'm going to push this soon if no objections. BR, Kewen ----- PR target/111367 gcc/ChangeLog: * config/rs6000/rs6000.md (stack_protect_setsi): Support prefixed instruction emission and incorporate to stack_protect_set. (stack_protect_setdi): Rename to ... (stack_protect_set): ... this, adjust constraint. (stack_protect_testsi): Support prefixed instruction emission and incorporate to stack_protect_test. (stack_protect_testdi): Rename to ... (stack_protect_test): ... this, adjust constraint. gcc/testsuite/ChangeLog: * g++.target/powerpc/pr111367.C: New test. --- gcc/config/rs6000/rs6000.md | 73 ++++++++------------- gcc/testsuite/g++.target/powerpc/pr111367.C | 22 +++++++ 2 files changed, 49 insertions(+), 46 deletions(-) create mode 100644 gcc/testsuite/g++.target/powerpc/pr111367.C -- 2.40.1 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1a9a7b1a479..0ac79fc7735 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -12389,33 +12389,26 @@ (define_expand "stack_protect_set" DONE; }) -(define_insn "stack_protect_setsi" - [(set (match_operand:SI 0 "memory_operand" "=m") - (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) - (set (match_scratch:SI 2 "=&r") (const_int 0))] - "TARGET_32BIT" - "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0" - [(set_attr "type" "three") - (set_attr "length" "12")]) - ;; We can't use the prefixed attribute here because there are two memory ;; instructions. We can't split the insn due to the fact that this operation ;; needs to be done in one piece. -(define_insn "stack_protect_setdi" - [(set (match_operand:DI 0 "memory_operand" "=Y") - (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET)) - (set (match_scratch:DI 2 "=&r") (const_int 0))] - "TARGET_64BIT" +(define_insn "stack_protect_set" + [(set (match_operand:P 0 "memory_operand" "=YZ") + (unspec:P [(match_operand:P 1 "memory_operand" "YZ")] UNSPEC_SP_SET)) + (set (match_scratch:P 2 "=&r") (const_int 0))] + "" { - if (prefixed_memory (operands[1], DImode)) - output_asm_insn ("pld %2,%1", operands); + if (prefixed_memory (operands[1], mode)) + /* Prefixed load only supports D-form but no update and X-form. */ + output_asm_insn ("p %2,%1", operands); else - output_asm_insn ("ld%U1%X1 %2,%1", operands); + output_asm_insn ("%U1%X1 %2,%1", operands); - if (prefixed_memory (operands[0], DImode)) - output_asm_insn ("pstd %2,%0", operands); + if (prefixed_memory (operands[0], mode)) + /* Prefixed store only supports D-form but no update and X-form. */ + output_asm_insn ("pst %2,%0", operands); else - output_asm_insn ("std%U0%X0 %2,%0", operands); + output_asm_insn ("st%U0%X0 %2,%0", operands); return "li %2,0"; } @@ -12461,45 +12454,33 @@ (define_expand "stack_protect_test" DONE; }) -(define_insn "stack_protect_testsi" - [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") - (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m") - (match_operand:SI 2 "memory_operand" "m,m")] - UNSPEC_SP_TEST)) - (set (match_scratch:SI 4 "=r,r") (const_int 0)) - (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_32BIT" - "@ - lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 - lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0" - [(set_attr "length" "16,20")]) - ;; We can't use the prefixed attribute here because there are two memory ;; instructions. We can't split the insn due to the fact that this operation ;; needs to be done in one piece. -(define_insn "stack_protect_testdi" +(define_insn "stack_protect_test" [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") - (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y") - (match_operand:DI 2 "memory_operand" "Y,Y")] + (unspec:CCEQ [(match_operand:P 1 "memory_operand" "YZ,YZ") + (match_operand:P 2 "memory_operand" "YZ,YZ")] UNSPEC_SP_TEST)) - (set (match_scratch:DI 4 "=r,r") (const_int 0)) - (clobber (match_scratch:DI 3 "=&r,&r"))] - "TARGET_64BIT" + (set (match_scratch:P 4 "=r,r") (const_int 0)) + (clobber (match_scratch:P 3 "=&r,&r"))] + "" { - if (prefixed_memory (operands[1], DImode)) - output_asm_insn ("pld %3,%1", operands); + if (prefixed_memory (operands[1], mode)) + /* Prefixed load only supports D-form but no update and X-form. */ + output_asm_insn ("p %3,%1", operands); else - output_asm_insn ("ld%U1%X1 %3,%1", operands); + output_asm_insn ("%U1%X1 %3,%1", operands); - if (prefixed_memory (operands[2], DImode)) - output_asm_insn ("pld %4,%2", operands); + if (prefixed_memory (operands[2], mode)) + output_asm_insn ("p %4,%2", operands); else - output_asm_insn ("ld%U2%X2 %4,%2", operands); + output_asm_insn ("%U2%X2 %4,%2", operands); if (which_alternative == 0) output_asm_insn ("xor. %3,%3,%4", operands); else - output_asm_insn ("cmpld %0,%3,%4\;li %3,0", operands); + output_asm_insn ("cmpl %0,%3,%4\;li %3,0", operands); return "li %4,0"; } diff --git a/gcc/testsuite/g++.target/powerpc/pr111367.C b/gcc/testsuite/g++.target/powerpc/pr111367.C new file mode 100644 index 00000000000..8f9d4415672 --- /dev/null +++ b/gcc/testsuite/g++.target/powerpc/pr111367.C @@ -0,0 +1,22 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -fstack-protector-strong" } */ + +/* Verify object file can be generated successfully. */ + +struct SortAscending +{ +}; + +typedef unsigned long long size_t; + +void VQSort (long long *, size_t, SortAscending); + +void +BenchAllColdSort () +{ + typedef long long T; + constexpr size_t kSize = 10 * 1000; + alignas (16) T items[kSize]; + VQSort (items, kSize, SortAscending ()); +}