diff --git a/gcc/combine.cc b/gcc/combine.cc
index a5fabf397f7..e1c1aa7da1c 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -11599,6 +11599,48 @@ change_zero_ext (rtx pat)
   return changed;
 }

+/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is
+   ASHIFT/AND, convert a pseudo to pseudo AND with a mask if its nonzero_bits
+   is less than its mode mask.  The nonzero_bits in later passes is not a
+   superset of what is known in combine pass.  So an insn with nonzero_bits
+   can't be recoged later.  */
+static bool
+change_pseudo_and_mask (rtx pat)
+{
+  rtx src = SET_SRC (pat);
+  if ((GET_CODE (src) == IOR
+       || GET_CODE (src) == XOR
+       || GET_CODE (src) == PLUS)
+      && (((GET_CODE (XEXP (src, 0)) == ASHIFT
+	    || GET_CODE (XEXP (src, 0)) == AND)
+	   && REG_P (XEXP (src, 1)))))
+    {
+      rtx reg = XEXP (src, 1);
+      machine_mode mode = GET_MODE (reg);
+      unsigned HOST_WIDE_INT nonzero = nonzero_bits (reg, mode);
+      if (nonzero < GET_MODE_MASK (mode))
+	{
+	  int shift;
+
+	  if (GET_CODE (XEXP (src, 0)) == ASHIFT)
+	    shift = INTVAL (XEXP (XEXP (src, 0), 1));
+	  else
+	    shift = ctz_hwi (INTVAL (XEXP (XEXP (src, 0), 1)));
+
+	  if (shift > 0
+	      && (HOST_WIDE_INT_1U << shift) - 1 >= nonzero)
+	    {
+	      unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << shift) - 1;
+	      rtx x = gen_rtx_AND (mode, reg, GEN_INT (mask));
+	      SUBST (XEXP (SET_SRC (pat), 1), x);
+	      maybe_swap_commutative_operands (SET_SRC (pat));
+	      return true;
+	    }
+	}
+    }
+  return false;
+}
+
 /* Like recog, but we receive the address of a pointer to a new pattern.
    We try to match the rtx that the pointer points to.
    If that fails, we may try to modify or replace the pattern,
@@ -11646,7 +11688,10 @@ recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
 	    }
 	}
       else
-	changed = change_zero_ext (pat);
+	{
+	  changed = change_pseudo_and_mask (pat);
+	  changed |= change_zero_ext (pat);
+	}
     }
   else if (GET_CODE (pat) == PARALLEL)
     {
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1367a2cb779..2bd6bd5f908 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4207,24 +4207,6 @@ (define_insn_and_split "*rotl<mode>3_insert_3_<code>"
 	(ior:GPR (and:GPR (match_dup 3) (match_dup 4))
 		 (ashift:GPR (match_dup 1) (match_dup 2))))])

-(define_code_iterator plus_ior_xor [plus ior xor])
-
-(define_split
-  [(set (match_operand:GPR 0 "gpc_reg_operand")
-	(plus_ior_xor:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
-				      (match_operand:SI 2 "const_int_operand"))
-			  (match_operand:GPR 3 "gpc_reg_operand")))]
-  "nonzero_bits (operands[3], <MODE>mode)
-   < HOST_WIDE_INT_1U << INTVAL (operands[2])"
-  [(set (match_dup 0)
-	(ior:GPR (and:GPR (match_dup 3)
-			  (match_dup 4))
-		 (ashift:GPR (match_dup 1)
-			     (match_dup 2))))]
-{
-  operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1);
-})
-
 (define_insn "*rotlsi3_insert_4"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr93453-2.c b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c
new file mode 100644
index 00000000000..a83a6511653
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr93453-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long foo (char a, long b)
+{
+  long c = a;
+  c = c | (b << 12);
+  return c;
+}
+
+long bar (long b, char a)
+{
+  long c = a;
+  long m = -4096;
+  c = c | (b & m);
+  return c;
+}
+
+/* { dg-final { scan-assembler-times {\mrl[wd]imi\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
index bafa371db73..d4dadacc6cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
@@ -8,8 +8,7 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */

-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */

