RISC-V: Allow all const_vec_duplicates as constants.

  Hi,

as we can always broadcast an integer constant to a vector register
allow them in riscv_const_insns.  We need as many instructions as
it takes to generate the constant and one vmv.vx.

Regards
 Robin

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_const_insns): Allow
	const_vec_duplicates.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Add vmv.v.x
	tests.
	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Dito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Dito.
---
 gcc/config/riscv/riscv.cc                     | 22 ++++--
 .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c    |  3 +-
 .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c    |  3 +-
 .../riscv/rvv/autovec/vmv-imm-run.c           |  8 ++
 .../riscv/rvv/autovec/vmv-imm-rv32.c          |  3 +-
 .../riscv/rvv/autovec/vmv-imm-rv64.c          |  3 +-
 .../riscv/rvv/autovec/vmv-imm-template.h      | 74 ++++++++++---------
 7 files changed, 73 insertions(+), 43 deletions(-)
  

Lgtm

Robin Dapp <rdapp@ventanamicro.com> 於 2023年5月26日 週五 22:10 寫道：

> Hi,
>
> as we can always broadcast an integer constant to a vector register
> allow them in riscv_const_insns.  We need as many instructions as
> it takes to generate the constant and one vmv.vx.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_const_insns): Allow
>         const_vec_duplicates.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Add vmv.v.x
>         tests.
>         * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Dito.
>         * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
>         * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Dito.
>         * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Dito.
>         * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Dito.
> ---
>  gcc/config/riscv/riscv.cc                     | 22 ++++--
>  .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c    |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c    |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-run.c           |  8 ++
>  .../riscv/rvv/autovec/vmv-imm-rv32.c          |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-rv64.c          |  3 +-
>  .../riscv/rvv/autovec/vmv-imm-template.h      | 74 ++++++++++---------
>  7 files changed, 73 insertions(+), 43 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index c2acab08b89..5e0b515fe7a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1297,12 +1297,22 @@ riscv_const_insns (rtx x)
>               }
>           }
>
> -       /* Constants from -16 to 15 can be loaded with vmv.v.i.
> -          The Wc0, Wc1 constraints are already covered by the
> -          vi constraint so we do not need to check them here
> -          separately.  */
> -       if (satisfies_constraint_vi (x))
> -         return 1;
> +       rtx elt;
> +       if (const_vec_duplicate_p (x, &elt))
> +         {
> +           /* Constants from -16 to 15 can be loaded with vmv.v.i.
> +              The Wc0, Wc1 constraints are already covered by the
> +              vi constraint so we do not need to check them here
> +              separately.  */
> +           if (satisfies_constraint_vi (x))
> +             return 1;
> +
> +           /* A const duplicate vector can always be broadcast from
> +              a general-purpose register.  This means we need as many
> +              insns as it takes to load the constant into the GPR
> +              and one vmv.v.x.  */
> +           return 1 + riscv_integer_cost (INTVAL (elt));
> +         }
>
>         /* TODO: We may support more const vector in the future.  */
>         return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> index 631ea3bf268..e8d017f7339 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> index 7ded6cc18d2..f85ad4117d3 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> index 22b1958af81..79099a37bdd 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
> @@ -53,4 +53,12 @@ int main ()
>    TEST_POS(uint64_t, 13)
>    TEST_POS(uint64_t, 14)
>    TEST_POS(uint64_t, 15)
> +  TEST_POS(uint32_t, 16)
> +  TEST_POS(uint32_t, 123)
> +  TEST_POS(uint32_t, 255)
> +  TEST_POS(uint32_t, 999)
> +  TEST_POS(uint32_t, 32701)
> +  TEST_POS(uint32_t, 65535)
> +  TEST_POS(uint32_t, 65536)
> +  TEST_POS(uint32_t, 923423)
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> index c419256cd45..6843bc6018d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
> index e386166f95e..39fb2a6cc7b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
> @@ -3,4 +3,5 @@
>
>  #include "vmv-imm-template.h"
>
> -/* { dg-final { scan-assembler-times "vmv.v.i" 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.i} 32 } } */
> +/* { dg-final { scan-assembler-times {vmv.v.x} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h
> index 855343d7e3e..84b26e0f1c2 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h
> @@ -17,38 +17,46 @@
>        dst[i] = -VAL;                                   \
>    }
>
> -#define TEST_ALL()     \
> -VMV_NEG(int8_t,16)     \
> -VMV_NEG(int8_t,15)     \
> -VMV_NEG(int8_t,14)     \
> -VMV_NEG(int8_t,13)     \
> -VMV_NEG(int16_t,12)     \
> -VMV_NEG(int16_t,11)     \
> -VMV_NEG(int16_t,10)     \
> -VMV_NEG(int16_t,9)     \
> -VMV_NEG(int32_t,8)     \
> -VMV_NEG(int32_t,7)     \
> -VMV_NEG(int32_t,6)     \
> -VMV_NEG(int32_t,5)     \
> -VMV_NEG(int64_t,4)     \
> -VMV_NEG(int64_t,3)     \
> -VMV_NEG(int64_t,2)     \
> -VMV_NEG(int64_t,1)     \
> -VMV_POS(uint8_t,0)     \
> -VMV_POS(uint8_t,1)     \
> -VMV_POS(uint8_t,2)     \
> -VMV_POS(uint8_t,3)     \
> -VMV_POS(uint16_t,4)    \
> -VMV_POS(uint16_t,5)    \
> -VMV_POS(uint16_t,6)    \
> -VMV_POS(uint16_t,7)    \
> -VMV_POS(uint32_t,8)    \
> -VMV_POS(uint32_t,9)    \
> -VMV_POS(uint32_t,10)   \
> -VMV_POS(uint32_t,11)   \
> -VMV_POS(uint64_t,12)   \
> -VMV_POS(uint64_t,13)   \
> -VMV_POS(uint64_t,14)   \
> -VMV_POS(uint64_t,15)
> +#define TEST_ALL()       \
> +VMV_NEG(int8_t,16)       \
> +VMV_NEG(int8_t,15)       \
> +VMV_NEG(int8_t,14)       \
> +VMV_NEG(int8_t,13)       \
> +VMV_NEG(int16_t,12)       \
> +VMV_NEG(int16_t,11)       \
> +VMV_NEG(int16_t,10)       \
> +VMV_NEG(int16_t,9)       \
> +VMV_NEG(int32_t,8)       \
> +VMV_NEG(int32_t,7)       \
> +VMV_NEG(int32_t,6)       \
> +VMV_NEG(int32_t,5)       \
> +VMV_NEG(int64_t,4)       \
> +VMV_NEG(int64_t,3)       \
> +VMV_NEG(int64_t,2)       \
> +VMV_NEG(int64_t,1)       \
> +VMV_POS(uint8_t,0)       \
> +VMV_POS(uint8_t,1)       \
> +VMV_POS(uint8_t,2)       \
> +VMV_POS(uint8_t,3)       \
> +VMV_POS(uint16_t,4)      \
> +VMV_POS(uint16_t,5)      \
> +VMV_POS(uint16_t,6)      \
> +VMV_POS(uint16_t,7)      \
> +VMV_POS(uint32_t,8)      \
> +VMV_POS(uint32_t,9)      \
> +VMV_POS(uint32_t,10)     \
> +VMV_POS(uint32_t,11)     \
> +VMV_POS(uint64_t,12)     \
> +VMV_POS(uint64_t,13)     \
> +VMV_POS(uint64_t,14)     \
> +VMV_POS(uint64_t,15)     \
> +VMV_POS(uint32_t,16)     \
> +VMV_POS(uint32_t,123)     \
> +VMV_POS(uint32_t,255)     \
> +VMV_POS(uint32_t,999)     \
> +VMV_POS(uint32_t,32701)   \
> +VMV_POS(uint32_t,65535)   \
> +VMV_POS(uint32_t,65536)   \
> +VMV_POS(uint32_t,923423)  \
>
>  TEST_ALL()
> --
> 2.40.1
>