From patchwork Thu Jun 22 13:03:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Dapp X-Patchwork-Id: 111657 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp5051283vqr; Thu, 22 Jun 2023 06:05:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6xWgiJID6AEJBd1brYTTNDL1NEpRq0cICYemgGqzBBsV22lCnQClkZg8tEnPFw5qDZsVcp X-Received: by 2002:aa7:db8d:0:b0:514:9929:1b01 with SMTP id u13-20020aa7db8d000000b0051499291b01mr12250801edt.8.1687439117268; Thu, 22 Jun 2023 06:05:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687439117; cv=none; d=google.com; s=arc-20160816; b=qqRr1EpSyK8NVhAMQJx7nSp3cM0HSW6pc4YaXbFF9PEAEq5OSnml2T6R9Bgl3B/6UK YLlGpqqgIom39SMRtaxIa030swczRBojk23I7fApsb8F6vPU5BMU8j4X3Oro7VCxcH30 0Ttb8/LD7c0Ep8FEHHl4bZyYQttFJWSNQPiQQ5GvkpfRIMsTILD/4xBWSoXcdc+4P3KO wogs2Djqh3JgpZNidUYLF3AAW57MfanRzBh5jSWxtb+z/dqb0Knj5+hTQuIX/TifwPUM zhi2YB+TNzkfs+u1daB52MOdas9xCq6jidGVbCYlXyM9sxnQvf9knPf0trAd4RkgjFrO dC4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:to:subject:content-language:cc:user-agent :mime-version:date:message-id:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=2Nqq8yW65iYRrPsi/xk9p4EpHR7iZkeOpwafiyKXlL8=; b=pc6MlIvqXQyxCD+uugwkg6amHJmXXPNL3M+LnWX0TqyIm8eiipZsdep28TXgk4dDNs 8Y3QQSgH0uLyj3BIsVbGn3EZRaA+6vXCJ5Iw1ikLpNMcXDAtQBMRtC8hY76i9GeHF1+4 j+ANmgnY4Ztehu56K30MNaFoUS8PlZYseb3hyuwHY8FHejXiCMccGf8KzJ86l9ftfrce z8b6EIvmfeKG3SDbklANsDtda6oi2JCJgMCWMrr1ICgWgPO4C5pgM175IqziEy/Yl4iU 3d58NzbeusoNBWQ8UOHQ/WjF2bik8+K+bqnvc/uWUjR4rRdkO+QOLgDQuZM5nE+4GPvX YaRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=tA8OdQpr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ba15-20020a0564021acf00b0051a43a9b018si348130edb.36.2023.06.22.06.05.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 06:05:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=tA8OdQpr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9318F3858024 for ; Thu, 22 Jun 2023 13:04:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9318F3858024 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687439073; bh=2Nqq8yW65iYRrPsi/xk9p4EpHR7iZkeOpwafiyKXlL8=; h=Date:Cc:Subject:To:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=tA8OdQprtqaSDFrGZ4bCnn+MflYTqKk20VWAEFfCDt5mQSbRyPcOPM1BPhYDstlIK 9V0c/CURCc+W6qfRohRs7bu2pxyoyRF7lZotaYfROwBgTOZkBiqt2aXWS5bS6V9NN2 nAymmIj2KFaarrzGh1/PGO+AIMO+ETDVoUS6gPyg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id 38F173858D37 for ; Thu, 22 Jun 2023 13:03:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 38F173858D37 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-307d20548adso6000193f8f.0 for ; Thu, 22 Jun 2023 06:03:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687439023; x=1690031023; h=content-transfer-encoding:to:subject:from:content-language:cc :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2Nqq8yW65iYRrPsi/xk9p4EpHR7iZkeOpwafiyKXlL8=; b=kfeEJ8HY6pkE4jSnbIVca5hXLJVGg0GxThKckW40tW+flwIkjFjrmXtsKmFEi7DVWu MLYURL+HczSV74AtS6/p935Sdd18labI5Kq+BfqlvOcA46a1AvJ+JlPLRo9omHi0AHZW RoQXzM/Vk5rd0h0sCsMOo+XxOpGiGTSI5UNmjYRmPM1dUcFP3/O34SdcTm54fbhadLoL 0CoKzudX3NNcFPuGaROjO8hAEmLBwfRmnU9+Bjct8+Sv2soGvQvgbSDnbC/EzIFYSqwQ XoxA0J9JUVa+ECaO81LuUmR/r6lojE4Glg1dKSPlNqaHUER/ssoG5x3jYsKhQkYQaOh7 skCA== X-Gm-Message-State: AC+VfDzWGUcQxHrqNfaQIxb2ofxaR/ydvI0eIPVPJ045tyiHnfG0O/kY t5nyPSlaXtRZMEqKGE1sN/yfQ2tnIrg= X-Received: by 2002:adf:f150:0:b0:30a:e954:3d99 with SMTP id y16-20020adff150000000b0030ae9543d99mr13100610wro.58.1687439023149; Thu, 22 Jun 2023 06:03:43 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id m4-20020a5d56c4000000b003078354f774sm6997830wrw.36.2023.06.22.06.03.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jun 2023 06:03:42 -0700 (PDT) Message-ID: Date: Thu, 22 Jun 2023 15:03:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US Subject: [PATCH] RISC-V: Split VF iterators for Zvfh(min). To: gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , "Li, Pan2" , jeffreyalaw X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769408159561561592?= X-GMAIL-MSGID: =?utf-8?q?1769408159561561592?= Hi, when working on FP widening/narrowing I realized the Zvfhmin handling is not ideal right now: We use the "enabled" insn attribute to disable instructions not available with Zvfhmin (but only with Zvfh). However, "enabled == 0" only disables insn alternatives, in our case all of them when the mode is a HFmode. The insn itself remains available (e.g. for combine to match) and we end up with an insn without alternatives that reload cannot handle --> ICE. The proper solution is to disable the instruction for the respective mode altogether. This patch achieves this by splitting the VF as well as VWEXTF iterators into variants with TARGET_ZVFH and TARGET_VECTOR_ELEN_FP_16 (which is true when either TARGET_ZVFH or TARGET_ZVFHMIN are true). Also, VWCONVERTI, VHF and VHF_LMUL1 need adjustments. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md: VF_AUTO -> VF. * config/riscv/vector-iterators.md: Introduce VF_ZVFHMIN, VWEXTF_ZVFHMIN and use TARGET_ZVFH in VWCONVERTI, VHF and VHF_LMUL1. * config/riscv/vector.md: Use new iterators. --- gcc/config/riscv/autovec.md | 28 ++++++------- gcc/config/riscv/vector-iterators.md | 63 ++++++++++++++++++---------- gcc/config/riscv/vector.md | 20 ++++----- 3 files changed, 64 insertions(+), 47 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f1641d7e1ea..7f0b2befd6b 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -539,9 +539,9 @@ (define_expand "abs2" ;; - vfneg.v/vfabs.v ;; ------------------------------------------------------------------------------- (define_expand "2" - [(set (match_operand:VF_AUTO 0 "register_operand") - (any_float_unop_nofrm:VF_AUTO - (match_operand:VF_AUTO 1 "register_operand")))] + [(set (match_operand:VF 0 "register_operand") + (any_float_unop_nofrm:VF + (match_operand:VF 1 "register_operand")))] "TARGET_VECTOR" { insn_code icode = code_for_pred (, mode); @@ -556,9 +556,9 @@ (define_expand "2" ;; - vfsqrt.v ;; ------------------------------------------------------------------------------- (define_expand "2" - [(set (match_operand:VF_AUTO 0 "register_operand") - (any_float_unop:VF_AUTO - (match_operand:VF_AUTO 1 "register_operand")))] + [(set (match_operand:VF 0 "register_operand") + (any_float_unop:VF + (match_operand:VF 1 "register_operand")))] "TARGET_VECTOR" { insn_code icode = code_for_pred (, mode); @@ -777,10 +777,10 @@ (define_expand "vec_extract" ;; - vfadd.vf/vfsub.vf/... ;; ------------------------------------------------------------------------- (define_expand "3" - [(match_operand:VF_AUTO 0 "register_operand") - (any_float_binop:VF_AUTO - (match_operand:VF_AUTO 1 "register_operand") - (match_operand:VF_AUTO 2 "register_operand"))] + [(match_operand:VF 0 "register_operand") + (any_float_binop:VF + (match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand"))] "TARGET_VECTOR" { riscv_vector::emit_vlmax_fp_insn (code_for_pred (, mode), @@ -794,10 +794,10 @@ (define_expand "3" ;; - vfmin.vf/vfmax.vf ;; ------------------------------------------------------------------------- (define_expand "3" - [(match_operand:VF_AUTO 0 "register_operand") - (any_float_binop_nofrm:VF_AUTO - (match_operand:VF_AUTO 1 "register_operand") - (match_operand:VF_AUTO 2 "register_operand"))] + [(match_operand:VF 0 "register_operand") + (any_float_binop_nofrm:VF + (match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand"))] "TARGET_VECTOR" { riscv_vector::emit_vlmax_insn (code_for_pred (, mode), diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 6ca1c54c709..ae9f44b5f78 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -271,7 +271,7 @@ (define_mode_iterator VWI [ (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") ]) -(define_mode_iterator VF [ +(define_mode_iterator VF_ZVFHMIN [ (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") (VNx4HF "TARGET_VECTOR_ELEN_FP_16") @@ -295,11 +295,12 @@ (define_mode_iterator VF [ ;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16 ;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for -;; TARGET_ZVFHMIN while we actually disable all instructions apart from -;; load, store and convert for it. -;; Consequently the autovec expanders should also only be enabled with -;; TARGET_ZVFH. -(define_mode_iterator VF_AUTO [ +;; TARGET_ZVFHMIN while we actually want to disable all instructions apart +;; from load, store and convert for it. +;; It is not enough to set the "enabled" attribute to false +;; since this will only disable insn alternatives in reload but still +;; allow the instruction and mode to be matched during combine et al. +(define_mode_iterator VF [ (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_ZVFH") (VNx4HF "TARGET_ZVFH") @@ -494,7 +495,8 @@ (define_mode_iterator VWEXTI [ (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") ]) -(define_mode_iterator VWEXTF [ +;; Same iterator split reason as VF_ZVFHMIN and VF. +(define_mode_iterator VWEXTF_ZVFHMIN [ (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_16") (VNx4SF "TARGET_VECTOR_ELEN_FP_16") @@ -509,13 +511,28 @@ (define_mode_iterator VWEXTF [ (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") ]) +(define_mode_iterator VWEXTF [ + (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SF "TARGET_ZVFH") + (VNx4SF "TARGET_ZVFH") + (VNx8SF "TARGET_ZVFH") + (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") + (VNx2DF "TARGET_VECTOR_ELEN_FP_64") + (VNx4DF "TARGET_VECTOR_ELEN_FP_64") + (VNx8DF "TARGET_VECTOR_ELEN_FP_64") + (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128") +]) + (define_mode_iterator VWCONVERTI [ - (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16") - (VNx2SI "TARGET_VECTOR_ELEN_FP_16") - (VNx4SI "TARGET_VECTOR_ELEN_FP_16") - (VNx8SI "TARGET_VECTOR_ELEN_FP_16") - (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") - (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16") + (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2SI "TARGET_ZVFH") + (VNx4SI "TARGET_ZVFH") + (VNx8SI "TARGET_ZVFH") + (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32") @@ -992,13 +1009,13 @@ (define_mode_iterator VDI [ ]) (define_mode_iterator VHF [ - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") - (VNx8HF "TARGET_VECTOR_ELEN_FP_16") - (VNx16HF "TARGET_VECTOR_ELEN_FP_16") - (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_ZVFH") + (VNx4HF "TARGET_ZVFH") + (VNx8HF "TARGET_ZVFH") + (VNx16HF "TARGET_ZVFH") + (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VSF [ @@ -1042,9 +1059,9 @@ (define_mode_iterator VDI_LMUL1 [ ]) (define_mode_iterator VHF_LMUL1 [ - (VNx8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32") + (VNx8HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (VNx4HF "TARGET_ZVFH && TARGET_MIN_VLEN == 64") + (VNx2HF "TARGET_ZVFH && TARGET_MIN_VLEN == 32") ]) (define_mode_iterator VSF_LMUL1 [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 884e7435cc2..11ed851a564 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1351,8 +1351,8 @@ (define_insn_and_split "*pred_broadcast" (set_attr "mode" "")]) (define_insn "*pred_broadcast" - [(set (match_operand:VF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr") - (if_then_else:VF + [(set (match_operand:VF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr") + (if_then_else:VF_ZVFHMIN (unspec: [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") @@ -1361,9 +1361,9 @@ (define_insn "*pred_broadcast" (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (vec_duplicate:VF + (vec_duplicate:VF_ZVFHMIN (match_operand: 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f")) - (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand:VF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "@ vfmv.v.f\t%0,%3 @@ -7106,8 +7106,8 @@ (define_insn "@pred_widen_" (set_attr "mode" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") - (if_then_else:VWEXTF + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr") + (if_then_else:VWEXTF_ZVFHMIN (unspec: [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 4 "vector_length_operand" " rK, rK") @@ -7116,9 +7116,9 @@ (define_insn "@pred_extend" (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (float_extend:VWEXTF + (float_extend:VWEXTF_ZVFHMIN (match_operand: 3 "register_operand" " vr, vr")) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") @@ -7206,7 +7206,7 @@ (define_insn "@pred_trunc" (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (float_truncate: - (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfncvt.f.f.w\t%0,%3%p1" @@ -7226,7 +7226,7 @@ (define_insn "@pred_rod_trunc" (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [(float_truncate: - (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD) + (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" "vfncvt.rod.f.f.w\t%0,%3%p1"