diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bc8bc6ab060..b0b40f91e3e 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4253,6 +4253,36 @@ (define_insn "*rotl<mode>3_insert"
 ; difference between rlwimi and rldimi.  We also might want dot forms,
 ; but not for rlwimi on POWER4 and similar processors.

+; Subreg pattern of insn "*rotlsi3_insert"
+(define_insn_and_split "*rotlsi3_insert_9"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI
+		 (match_operator:SI 8 "lowpart_subreg_operator"
+		  [(and:DI (match_operator:DI 4 "rotate_mask_operator"
+			    [(match_operand:DI 1 "gpc_reg_operand" "r")
+			     (match_operand:SI 2 "const_int_operand" "n")])
+			   (match_operand:DI 3 "const_int_operand" "n"))])
+		 (match_operand:SI 5 "const_int_operand" "n"))
+		(and:SI (match_operand:SI 6 "gpc_reg_operand" "0")
+			(match_operand:SI 7 "const_int_operand" "n"))))]
+  "rs6000_is_valid_insert_mask (operands[5], operands[4], SImode)
+   && GET_CODE (operands[4]) == LSHIFTRT
+   && INTVAL (operands[3]) == 0xffffffff
+   && UINTVAL (operands[5]) + UINTVAL (operands[7]) + 1 == 0"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(ior:SI (and:SI (lshiftrt:SI (match_dup 9)
+				     (match_dup 2))
+			(match_dup 5))
+		(and:SI (match_dup 6)
+			(match_dup 7))))]
+{
+  int offset = BYTES_BIG_ENDIAN ? 4 : 0;
+  operands[9] = gen_rtx_SUBREG (SImode, operands[1], offset);
+}
+  [(set_attr "type" "insert")])
+
 (define_insn "*rotl<mode>3_insert_2"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(ior:GPR (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0")
@@ -4331,6 +4361,31 @@ (define_insn "*rotlsi3_insert_4"
   "rlwimi %0,%1,32-%h2,%h2,31"
   [(set_attr "type" "insert")])

+; Subreg pattern of insn "*rotlsi3_insert_4"
+(define_insn_and_split "*rotlsi3_insert_8"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+			(match_operand:SI 4 "const_int_operand" "n"))
+		(match_operator:SI 6 "lowpart_subreg_operator"
+		  [(and:DI
+		    (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+				 (match_operand:SI 2 "const_int_operand" "n"))
+		    (match_operand:DI 5 "const_int_operand" "n"))])))]
+  "INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4])) == 32
+   && INTVAL (operands[5]) == 0xffffffff"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(ior:SI (and:SI (match_dup 3)
+			(match_dup 4))
+		(lshiftrt:SI (match_dup 7)
+			     (match_dup 2))))]
+{
+  int offset = BYTES_BIG_ENDIAN ? 4 : 0;
+  operands[7] = gen_rtx_SUBREG (SImode, operands[1], offset);
+}
+  [(set_attr "type" "insert")])
+
 (define_insn "*rotlsi3_insert_5"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0,r")
diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
index bafa371db73..62344a95aa0 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
@@ -6,10 +6,9 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6728 { target lp64 } } } */

-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
index 4f4fca2d8ef..a10d9174306 100644
--- a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c
@@ -4,10 +4,10 @@
 /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 6739 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 9716 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+blr} 3375 } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3081 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3090 { target lp64 } } } */

 /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3197 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3093 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3084 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 154 } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */
