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[committed,5/6] amdgcn: Add vector integer negate insn

Message ID bf6b5c74a6f1927174091c73aa51401895ef92f0.1665485382.git.ams@codesourcery.com
State New, archived
Headers
Series amdgcn: Add V32, V16, V8, V4, and V2 vectors |

Commit Message

Andrew Stubbs Oct. 11, 2022, 11:02 a.m. UTC 
  Another example of the vectorizer needing explicit insns where the scalar
expander just works.

gcc/ChangeLog:

	* config/gcn/gcn-valu.md (neg<mode>2): New define_expand.
---
 gcc/config/gcn/gcn-valu.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)
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Patch

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index f708e587f38..00c0e3be1ea 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2390,6 +2390,19 @@  (define_insn "<expander><vnsi>3<exec>"
   [(set_attr "type" "vop2,ds")
    (set_attr "length" "8,8")])
 
+;; }}}
+;; {{{ Int unops
+
+(define_expand "neg<mode>2"
+  [(match_operand:V_INT 0 "register_operand")
+   (match_operand:V_INT 1 "register_operand")]
+  ""
+  {
+    emit_insn (gen_sub<mode>3 (operands[0], gcn_vec_constant (<MODE>mode, 0),
+			       operands[1]));
+    DONE;
+  })
+
 ;; }}}
 ;; {{{ FP binops - special cases