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Rozycki" From: "Jie Mei" Message-Id: In-Reply-To: X-Lms-Return-Path: References: X-Mailer: git-send-email 2.40.1 To: Subject: [PATCH v4 7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 Date: Mon, 19 Jun 2023 16:29:56 +0800 Mime-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769119287616402224?= X-GMAIL-MSGID: =?utf-8?q?1769119287616402224?= The MIPS16e2 ASE has PREF, LL and SC instructions, they use 9 bits immediate, like mips32r6. The MIPS32 PRE-R6 uses 16 bits immediate. gcc/ChangeLog: * config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause for ISA_HAS_MIPS16E2. (ISA_HAS_SYNC): Same as above. (ISA_HAS_LL_SC): Same as above. --- gcc/config/mips/mips.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e09a6c60157..05ccd2061c7 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1248,7 +1248,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ -#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) +#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \ + || ISA_HAS_MIPS16E2) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. @@ -1341,7 +1342,8 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1350,7 +1352,8 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \