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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j11-20020aa7c40b000000b00459f9c3d02bsi15569764edq.22.2022.11.10.03.20.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 03:20:56 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Ubc7ri1W; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6B6143857C51 for ; Thu, 10 Nov 2022 11:20:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6B6143857C51 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668079255; bh=Itxr0i/22m7afyvxb8nIOVKnxTyxf/gGFvAldHLkaY0=; h=Date:Subject:To:Cc:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Ubc7ri1W4aeAZsERMA0wWfH++LimbvHt5XV7K/AMjsevQ+640WlHwojQok0ZChpmH 7VlhXX8Eb8cbfO/QP5X78Zrpk07FgDuYKq6xdtwXTwvXaZhvkuoBnPbru0CFaMOha8 t8SDBgMuKPPedvR4QOSQE5LUBm0Yws8/gM69d7/w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3FD853858D20 for ; Thu, 10 Nov 2022 11:20:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3FD853858D20 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F7581FB; Thu, 10 Nov 2022 03:20:14 -0800 (PST) Received: from [10.57.4.81] (unknown [10.57.4.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D9C93F534; Thu, 10 Nov 2022 03:20:07 -0800 (PST) Message-ID: Date: Thu, 10 Nov 2022 11:20:01 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: Kyrylo Tkachov , Richard Earnshaw , Richard Sandiford References: In-Reply-To: X-Spam-Status: No, score=-16.6 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749107874752755981?= X-GMAIL-MSGID: =?utf-8?q?1749107874752755981?= Hi, This patch adds support for the widening LDAPR instructions. Bootstrapped and regression tested on aarch64-none-linux-gnu. OK for trunk? 2022-11-09  Andre Vieira              Kyrylo Tkachov  gcc/ChangeLog:         * config/aarch64/atomics.md (*aarch64_atomic_load_rcpc_zext): New pattern.         (*aarch64_atomic_load_rcpc_zext): Likewise. gcc/testsuite/ChangeLog:         * gcc.target/aarch64/ldapr-ext.c: New test. diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 9a9a30945c6e482a81a1bf446fe05d5efc462d32..77e5b29ad2c41215aa1ca904efb990b087010cef 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -691,6 +691,28 @@ } ) +(define_insn "*aarch64_atomic_load_rcpc_zext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldapr\t%0, %1" +) + +(define_insn "*aarch64_atomic_load_rcpc_sext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (sign_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldaprs\t%0, %1" +) + (define_insn "atomic_store" [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust") (unspec_volatile:ALLI diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c new file mode 100644 index 0000000000000000000000000000000000000000..5a788ffb8787291d43fe200d1d7803b901186912 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -std=c99" } */ +/* { dg-require-effective-target aarch64_rcpc_ok } */ +/* { dg-add-options aarch64_rcpc } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +#include + +atomic_ullong u64; +atomic_llong s64; +atomic_uint u32; +atomic_int s32; +atomic_ushort u16; +atomic_short s16; +atomic_uchar u8; +atomic_schar s8; + +#define TEST(name, ldsize, rettype) \ +rettype \ +test_##name (void) \ +{ \ + return atomic_load_explicit (&ldsize, memory_order_acquire); \ +} + +/* +**test_u8_u64: +**... +** ldaprb x0, \[x[0-9]+\] +** ret +*/ + +TEST(u8_u64, u8, unsigned long long) + +/* +**test_s8_s64: +**... +** ldaprsb x0, \[x[0-9]+\] +** ret +*/ + +TEST(s8_s64, s8, long long) + +/* +**test_u16_u64: +**... +** ldaprh x0, \[x[0-9]+\] +** ret +*/ + +TEST(u16_u64, u16, unsigned long long) + +/* +**test_s16_s64: +**... +** ldaprsh x0, \[x[0-9]+\] +** ret +*/ + +TEST(s16_s64, s16, long long) + +/* +**test_u8_u32: +**... +** ldaprb w0, \[x[0-9]+\] +** ret +*/ + +TEST(u8_u32, u8, unsigned) + +/* +**test_s8_s32: +**... +** ldaprsb w0, \[x[0-9]+\] +** ret +*/ + +TEST(s8_s32, s8, int) + +/* +**test_u16_u32: +**... +** ldaprh w0, \[x[0-9]+\] +** ret +*/ + +TEST(u16_u32, u16, unsigned) + +/* +**test_s16_s32: +**... +** ldaprsh w0, \[x[0-9]+\] +** ret +*/ + +TEST(s16_s32, s16, int)