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Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-0.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782970023333455285 X-GMAIL-MSGID: 1782970023333455285 Verify, for the generic floating-point NE conditional-add operation, that if-conversion does *not* trigger at `-mbranch-cost=2' setting, which makes original branched code sequences cheaper than their branchless equivalents if-conversion would emit. gcc/testsuite/ * gcc.target/riscv/adddibfne.c: New test. * gcc.target/riscv/addsibfne.c: New test. --- gcc/testsuite/gcc.target/riscv/adddibfne.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibfne.c | 26 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) gcc-riscv-test-addccne-branch-generic.diff Index: gcc/gcc/testsuite/gcc.target/riscv/adddibfne.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/adddibfne.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y + z : y; +} + +/* Expect branched assembly like: + + feq.d a5,fa0,fa1 + bne a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/addsibfne.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/addsibfne.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsifne (double w, double x, int_t y, int_t z) +{ + return w != x ? y + z : y; +} + +/* Expect branched assembly like: + + feq.d a5,fa0,fa1 + bne a5,zero,.L2 + add[w] a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */