From patchwork Sun Nov 19 05:40:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 166697 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp1505893vqn; Sat, 18 Nov 2023 21:41:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IFIOuYLl/vXBeFrOTUn3uZFCIEQcGH6fPGcNuKy8zuMIeUyJ8Th12xeWZXAq6gw8pJ2GmCH X-Received: by 2002:ac8:5984:0:b0:418:1565:ed49 with SMTP id e4-20020ac85984000000b004181565ed49mr5515039qte.41.1700372472909; Sat, 18 Nov 2023 21:41:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700372472; cv=pass; d=google.com; s=arc-20160816; b=m0mHJAtRr3KESzbRpq+nmtUMCis9NNn5rOoAcD0P8TxOIwV74h1yFLU9GEmrwhO4SL wbQmZLaZowDhm1hDNgBMf4jsKrmKsHtrmYcFmT3VoMRPbN939AAlLhaFCK62sGW86WpB GF9QkvDeo5DnZiCR9BI7DR+ivpZmMaO6NVNi4n2uU7E9gGiDPH4j3d0gVKCKKjW+SDrD YFNDC2wfOkYGa3tldI0SRgD/KHVfaj5ANGi3VbRvll8ibo49PByTUYFgfFtrjD+sXGXf ucXlRSYuKUxIhIcwW3mfHp++gXo2Ac8xsUT4XhtxFngTKE+j/IQHz6T+1GvX9cs1wLcF PIAQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:user-agent :references:message-id:in-reply-to:subject:cc:to:from:date :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=Ihcsds6TrFe2prwTePdIXqyasJa9hy3iwG1SxklU8gE=; fh=dp1z4I3tVhinwswv7IAFxpunWK+Ws/fGQfmox9vHv3I=; b=Vhx3Exg32WAYj0jzo9zHnpsC40cECh2BqLtKN/D62uTj3JFxRDUATF90XP0rC3dk83 8U1ObDyKKAoqM6krcpov2SQ2zcNz2QJiatM9gk32vj/vYmBkr1kSX3KPQvU2zG+uClse XTXPxTfjW1Tuuc5kqq84N7N2piIU39uQaTSH0KpBJbvvVQ6FcTS9cV2NLErbvCJpk5Ro W9cm/DJlwwTcUQqKNSQ0gyRqalB7sM7YA3MZug42dd/bGQyeYL9tNAF9syizhwdx4aZk 7ZqsDlPj5tG8e+87tEYb7qc1P9SActhti/MQ+dzUeXzBS3zMXE9cqXLteJnYx4GpRgnc t+ow== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@embecosm.com header.s=google header.b=AzjoKrWa; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o16-20020a05622a045000b0041983479612si5036224qtx.628.2023.11.18.21.41.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Nov 2023 21:41:12 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@embecosm.com header.s=google header.b=AzjoKrWa; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A28FD3857C5B for ; Sun, 19 Nov 2023 05:41:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 17703385829B for ; Sun, 19 Nov 2023 05:40:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 17703385829B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 17703385829B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::62f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372435; cv=none; b=xDldfcIsZEF0wEfbdwqhSPJ3qw1O00UPFhyNzu5+X6N7Y3VEOFahbjepWtbEtygucLr/4wzkgFQN5kVKNreySGzINeNGxJQirRkpR4CrTiuk3UFUrZE8g951+cE48V0VJhRTeBjK3PXDqhYcE8T9kyQF3teGHt6vwbS6Rt+COig= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700372435; c=relaxed/simple; bh=L+ihn/IeX8OaZR87sTWw64dmBURxTZ+UU4xv7J3mqtI=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=aZ4yE7XK92KSIOiYouzne+evx5Rc6S+H6S3cYWVHjU5wMnr9ugwWWouSN4+Gav8S0AYqi7w0th9xKWmjZva4bQ1jPzYNFQhxPP9MbH7WlTCEhC566qn+/g9frBVrMtKMDhdPZZBHkbwU+qAzcYGTetyg4jQmFuYq7pKZsw+/p/I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9e1fb7faa9dso457149866b.2 for ; Sat, 18 Nov 2023 21:40:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1700372431; x=1700977231; darn=gcc.gnu.org; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Ihcsds6TrFe2prwTePdIXqyasJa9hy3iwG1SxklU8gE=; b=AzjoKrWahRUsfWrG5tpKS9qLAA/Yc+2u2/2zRCCJyjekLUvjnh0hx0LRUMC1btsjvG dAlEyw0N95SGe2Eovgt8bjjeqvN5LtzYR87LkaerLIDszwmFQ1Qi5Z1FV5ECDKjotxLJ XNj70k4QTPgbC+p+2TH1+ufvdX5z6lNzM9+k9Y1PU0q1KOfv6dFKMl+2MyNXtIqTBI3K INdopfyQvFmAFb7j1Uh3RuT03sSH9DgxNt9REHCpC9I4eYsRmzV4dWq8/WTUG6/bpP5c AaJtGx/WRv2CrYfDCEBdp4XtTn8fo76bx3wgBfpdkdbL2VMWtGvSI0cXBDYXD1e0btXC za2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700372431; x=1700977231; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Ihcsds6TrFe2prwTePdIXqyasJa9hy3iwG1SxklU8gE=; b=gZsV+9tGEKSy5ltx1uUhyFw7wiiCwfMKOCdLP2cKtiP4qyxYNxExi5LmByriU6b5vK Lmbel6Sf0m8S5+Wprv58peik1ARAk3jPiqThTX9gVooVv/jWoEgiahcJIW/jTd4RZh39 gHkDM1jjHSm10/vcfWrKkSeUE+KyUCTU24907mUDiU3aaWp3LWmqiUAP+4I1sPzNddxS 0OkPL8k6pM8UkLi/6gYbspkda/TqPkumqw5WiT0fYJEgmFr6SD3sQdbidHNTx+uXkjtb C6Q6S4Nm6tI5GXx2vHl0puxjJ+lp/EAyjNaKeNXeO60q+aEenSSup1d4+AjbRtSrr3Iz LT8A== X-Gm-Message-State: AOJu0Yz/J1Cf9nuwYECCBSDqdk8ychpQ9O1qptIPXZZfruHsrrV9wvkY /Srm0TBnItGhSmghme37pRZ7hK7rWQCJxQG3stqg6w== X-Received: by 2002:a17:907:3f22:b0:9e6:4156:af4f with SMTP id hq34-20020a1709073f2200b009e64156af4fmr3697582ejc.55.1700372430844; Sat, 18 Nov 2023 21:40:30 -0800 (PST) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id e9-20020a170906374900b009e6298fc683sm2525947ejc.41.2023.11.18.21.40.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 18 Nov 2023 21:40:30 -0800 (PST) Date: Sun, 19 Nov 2023 05:40:26 +0000 (GMT) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 24/44] RISC-V/testsuite: Add branchless cases for T-Head non-equality cond moves In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782969766086038227 X-GMAIL-MSGID: 1782969766086038227 Verify, for T-Head targets and the non-equality integer conditional-move operations, that if-conversion triggers via `noce_try_cmove' at `-mbranch-cost=2' setting, which makes branchless code sequences produced by if-conversion cheaper than their original branched equivalents, and that extraneous instructions such as SNEZ, etc. are not present in output. gcc/testsuite/ * gcc.target/riscv/movdige-thead.c: New test. * gcc.target/riscv/movdigeu-thead.c: New test. * gcc.target/riscv/movdigt-thead.c: New test. * gcc.target/riscv/movdigtu-thead.c: New test. * gcc.target/riscv/movdile-thead.c: New test. * gcc.target/riscv/movdileu-thead.c: New test. * gcc.target/riscv/movdilt-thead.c: New test. * gcc.target/riscv/movdiltu-thead.c: New test. * gcc.target/riscv/movsige-thead.c: New test. * gcc.target/riscv/movsigeu-thead.c: New test. * gcc.target/riscv/movsigt-thead.c: New test. * gcc.target/riscv/movsigtu-thead.c: New test. * gcc.target/riscv/movsile-thead.c: New test. * gcc.target/riscv/movsileu-thead.c: New test. * gcc.target/riscv/movsilt-thead.c: New test. * gcc.target/riscv/movsiltu-thead.c: New test. --- gcc/testsuite/gcc.target/riscv/movdige-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdigeu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdigt-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdigtu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdile-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdileu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdilt-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdiltu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsige-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsigeu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsigt-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsigtu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsile-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsileu-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsilt-thead.c | 26 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsiltu-thead.c | 26 ++++++++++++++++++++++++ 16 files changed, 416 insertions(+) gcc-riscv-expand-conditional-move-sfb-alu-thead-test-movcc.diff Index: gcc/gcc/testsuite/gcc.target/riscv/movdige-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdige-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdige (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + slt a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdigeu (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigt-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdigt (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdigtu (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdile-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdile-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdile (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdileu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdileu (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdilt-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdilt (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + slt a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef unsigned int __attribute__ ((mode (DI))) int_t; + +int_t +movdiltu (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsige-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsige-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsige (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + slt a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsigeu (int_t w, int_t x, int_t y, int_t z) +{ + return w >= x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigt-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsigt (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsigtu (int_t w, int_t x, int_t y, int_t z) +{ + return w > x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsile-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsile-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsile (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgt a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsileu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsileu (int_t w, int_t x, int_t y, int_t z) +{ + return w <= x ? y : z; +} + +/* Expect branchless assembly like: + + sgtu a0,a0,a1 + th.mvnez a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsilt-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsilt (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + slt a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */ Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu-thead.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu-thead.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef unsigned int __attribute__ ((mode (SI))) int_t; + +int_t +movsiltu (int_t w, int_t x, int_t y, int_t z) +{ + return w < x ? y : z; +} + +/* Expect branchless assembly like: + + sltu a0,a0,a1 + th.mveqz a2,a3,a0 + mv a0,a2 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */