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Rozycki" To: gcc-patches@gcc.gnu.org cc: Andrew Waterman , Jim Wilson , Kito Cheng , Palmer Dabbelt Subject: [PATCH 21/44] RISC-V: Also accept constants for T-Head cond-move data input operands In-Reply-To: Message-ID: References: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782969700235836828 X-GMAIL-MSGID: 1782969700235836828 There is no need for the requirement for conditional-move data input operands to be stricter for T-Head targets than for short forward branch targets and limit them to registers only. They are keyed according to the `sfb_alu_operand' predicate, which lets certain constants through. Such constants are already forced into a register for the `cons' operand in the analogous short forward branch case and we can force them for the `alt' operand and T-Head as well. This enables more opportunities for a branchless sequence to be produced. gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): Also accept constants for T-Head data input operands. --- gcc/config/riscv/riscv.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) gcc-riscv-expand-conditional-move-thead-alt.diff Index: gcc/gcc/config/riscv/riscv.cc =================================================================== --- gcc.orig/gcc/config/riscv/riscv.cc +++ gcc/gcc/config/riscv/riscv.cc @@ -4094,8 +4094,6 @@ riscv_expand_conditional_move (rtx dest, if (TARGET_XTHEADCONDMOV && GET_MODE_CLASS (mode) == MODE_INT - && reg_or_0_operand (cons, mode) - && reg_or_0_operand (alt, mode) && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode) && (GET_MODE (op0) == mode || CONST_INT_P (op0)) && (GET_MODE (op1) == mode || CONST_INT_P (op1)) @@ -4113,6 +4111,8 @@ riscv_expand_conditional_move (rtx dest, cases for extensions which are more general than SFB. But does mean we need to force CONS into a register at this point. */ cons = force_reg (mode, cons); + /* With XTheadCondMov we need to force ALT into a register too. */ + alt = force_reg (mode, alt); emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, cons, alt))); return true;