From patchwork Mon Oct 16 09:41:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 153285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3342519vqb; Mon, 16 Oct 2023 02:41:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH2udqBEwuFMJD6tIyZcLz3xPuvKOXQd3Xm5Fi96uHfgEQ18KoxtcXaCt9VO7Ix28esM0zZ X-Received: by 2002:a05:620a:1a29:b0:777:2864:9c56 with SMTP id bk41-20020a05620a1a2900b0077728649c56mr21085196qkb.42.1697449315538; Mon, 16 Oct 2023 02:41:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697449315; cv=pass; d=google.com; s=arc-20160816; b=0KM7BWgycCV+LBdce2+Y2q7Vt7hJTsAR2pedmjKc/anunUkiWFJXj4JTIjyweh/7HV 32mFM/2LGYRPkkSlkUfbgIUYvpu7AxpCL0plDFmmL1OO1j6xSzXcOv6NvRKmb5q1nOie GbtgOjbhwspWltnt6fPFD/PnhbwxF2LtXxt4jd7WmHemcVz1EsxaFUQdBBzv3fyKTYnx b1JXsc3qqqVac4qdpSW6SYien5uL/F0uuXfUL8IPOgT22ErAN5vZwz02qPZCS1fushto Cl5alWZ+vVBGNnFJypw0PqY4x5oYBnx4VIc/lUEMZUL725Qe3hUBmzZ+ZX/igBXySepU RH+g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:user-agent :message-id:subject:to:from:date:dkim-signature:arc-filter :dmarc-filter:delivered-to; bh=s8Hx8ojsArG1U0Qns+FA2OnXyaduO8yNfc+Wx2IH3NQ=; fh=hPrbWPhweUx4V0GV9uXJqbyAzg2ABmTz7kczrAQqMmM=; b=kiTUXN/MKllbqyTW8E8I0tPKvuWflnyuSPOX1JxZHdFFwNjHsPVt7NY/hDJWSTVC2v zJoERQUN8IV1yTBchIGi7X/Q7YQ1WXMSyMSCyIZLdsvgdeb7DcI+Y5OOLhbMgC76zcCE VFggGmwIwUZsQuMV0ci25kaaSR1ZkGj9Hd+9Bkra+JsqHDwRGQwV04L6+LD+r5dCxFJz tB2LMU8b+0E/v0S5RawtD0nOD9Sgdd6iZSNLwzscnZLt9oEmE1Yz2+8K644z3hQmGqI9 tMzk5cmoF6MsiJl3ItItGwv8+69OtbPym37sg3fa0CrYmbW0SEN2UXKtpkPzn7WDr1Gi wV+Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@embecosm.com header.s=google header.b="AJLtFgO/"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o14-20020ac85a4e000000b00406944090f6si5001611qta.222.2023.10.16.02.41.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 02:41:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@embecosm.com header.s=google header.b="AJLtFgO/"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 51799385781F for ; Mon, 16 Oct 2023 09:41:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by sourceware.org (Postfix) with ESMTPS id 8D4423858C2A for ; Mon, 16 Oct 2023 09:41:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D4423858C2A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8D4423858C2A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::52d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697449292; cv=none; b=aUi2F+0EKfZa6xAtITmxBha1KtAgYQK2bh2xezyEQphjmirPp/wY0p+gCR+lkKcNKqwnyKEEn8vYznM3uMuVr4ZkNWc+34MErOQyKb6BkKzK7Y6hT7BYvj6V03qAmU4xBVhfILbGGRPYXB9LLCy055W/4mxJS6ybPuMOKbSz7Io= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697449292; c=relaxed/simple; bh=B3ot7w5jFGg2aKiyNHL//laMvk1F7DK+dm/b+Aj6w7s=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=ipeYSAsaaGN//1ISTBxLzKveeGzdvTIVZ3doCAqbIUlTw4OBYviB0whKAycCaBd2CxAsdPcVRJmZjPLyQaz5mxSFnb5F725r2PhHUjfAM41s6AqlGGj+QlugG23urCqoWgj5DqJyIHdktz/VHyu1s1QB2GR3Y+MpVGRlYgebAWE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-53df747cfe5so7607098a12.2 for ; Mon, 16 Oct 2023 02:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1697449289; x=1698054089; darn=gcc.gnu.org; h=mime-version:user-agent:message-id:subject:to:from:date:from:to:cc :subject:date:message-id:reply-to; bh=s8Hx8ojsArG1U0Qns+FA2OnXyaduO8yNfc+Wx2IH3NQ=; b=AJLtFgO/JRb9zhflx6BJwdJe5+l7UgnCRPuecWw2NhjPGl7RYLCSVtkx9rrZ5CmTty c1BSams2VwCN0K3ytdxKu+DMZZr+cvTeUSrLv0tKDtcwbBAgG4tmsVrYdT6ktLQRY1/U jjFktVei8qmnNuccOTx0lv3IgXf3UO7YYXAw09NoJtplZ7OW7RhGgsFeEbb2zXmpOyH3 Ukzmgc17aYBQSLC14l/G8t/dksEvhJaZu2GV4V8TZwnCA1d1MVIuQod7kk8SrGZQrrjD 1us75CAuBYTK7oyxkY4z/sUWuFgYUnSmScwbhq4hZMW5z5sOcCSAHpkHarn1xjpb3l2p lwfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697449289; x=1698054089; h=mime-version:user-agent:message-id:subject:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=s8Hx8ojsArG1U0Qns+FA2OnXyaduO8yNfc+Wx2IH3NQ=; b=A0o44XcAxOg6CnDbeGGKonNKEUieLEcrccdFKJe6zAghbANDYXjSlyW916i2/e1RmP oFov5GlgCA8kjNhdwYuNlZxjq5r+oNUZ37QocNIOVh17vm4FsNzKABHdMYqDVE0wcLvu 9xr4kHCNoD8bJiCGTN2a246mF2XmmnWHmG99mlGIfWSWgXEnXr4JM32LiJOPgOab8qC/ 8UoHSoQCNcg01ID/leepKW456jr95yNnSZkBu9/ukaqfTM+OyWf0puupVC+nToNBuEDo 4lAjLcmalpnybs3HscgbeqVlQh6e7H60UKDgWCrXQR3hS3G5SfZlLs0UGwKDZUuiCvZy eqog== X-Gm-Message-State: AOJu0YzucP1APN1WWlpwX323KRNxMQ+Qj4TYtUd0Df1aKci7/EHjZyUY RpC94ewOQXgUQPMZSZbSfCIAWxdYERi7BvsiBaA= X-Received: by 2002:a05:6402:40c9:b0:53e:781c:da3d with SMTP id z9-20020a05640240c900b0053e781cda3dmr4481622edb.25.1697449289135; Mon, 16 Oct 2023 02:41:29 -0700 (PDT) Received: from annie.orcam.me.uk (annie.orcam.me.uk. [2001:4190:8020::48]) by smtp.gmail.com with ESMTPSA id u25-20020aa7db99000000b0053116e45317sm15159039edt.44.2023.10.16.02.41.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Oct 2023 02:41:28 -0700 (PDT) Date: Mon, 16 Oct 2023 10:41:26 +0100 (BST) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH RFA] PR target/111815: VAX: Only accept the index scaler as the RHS operand to ASHIFT Message-ID: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK, WEIRD_PORT autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779904613477442920 X-GMAIL-MSGID: 1779904613477442920 As from commit 9df1ba9a35b8 ("libbacktrace: support zstd decompression") GCC for the `vax-netbsdelf' target fails to complete building, with an ICE: during RTL pass: final .../libbacktrace/elf.c: In function 'elf_zstd_decompress': .../libbacktrace/elf.c:5006:1: internal compiler error: in print_operand_address, at config/vax/vax.cc:514 5006 | } | ^ 0x1113df97 print_operand_address(_IO_FILE*, rtx_def*) .../gcc/config/vax/vax.cc:514 0x10c2489b default_print_operand_address(_IO_FILE*, machine_mode, rtx_def*) .../gcc/targhooks.cc:373 0x106ddd0b output_address(machine_mode, rtx_def*) .../gcc/final.cc:3648 0x106ddd0b output_asm_insn(char const*, rtx_def**) .../gcc/final.cc:3505 0x106e2143 output_asm_insn(char const*, rtx_def**) .../gcc/final.cc:3421 0x106e2143 final_scan_insn_1 .../gcc/final.cc:2841 0x106e28e3 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) .../gcc/final.cc:2887 0x106e2bf7 final_1 .../gcc/final.cc:1979 0x106e3c67 rest_of_handle_final .../gcc/final.cc:4240 0x106e3c67 execute .../gcc/final.cc:4318 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See for instructions. This is due to combine producing an invalid address RTX: (plus:SI (ashift:SI (const_int 1 [0x1]) (reg:QI 3 %r3 [1232])) (reg/v:SI 10 %r10 [orig:736 weight_mask ] [736])) where the expression is ((1 << R3) + R10), which does not match a valid machine addressing mode. Consequently `print_operand_address' chokes. This can be reduced to the testcase included, where it triggers the same ICE in `p'. Preincrements are required so that their results land in registers and consequently an indexed addressing mode is tried or otherwise doing operations piecemeal on stack-based function arguments as direct input operands turns out more profitable in terms of RTX costs and the ICE is avoided. The ultimate cause has been commit c605a8bf9270 ("VAX: Accept ASHIFT in address expressions"), where a shift of an immediate value by a register has been mistakenly allowed as an index expression as if the shift operation was commutative such as multiplication is. So with ASHIFT the scaler in an index expression has to be the right-hand operand, and the backend has to enforce that, whereas with MULT the scaler can be either operand. Fix this by only accepting the index scaler as the RHS operand to ASHIFT. gcc/ PR target/111815 * config/vax/vax.cc (index_term_p): Only accept the index scaler as the RHS operand to ASHIFT. gcc/testsuite/ PR target/111815 * gcc.dg/torture/pr111815.c: New test. --- Hi, The testcase is generic enough I thought it wouldn't hurt to place it in a generic part of the testsuite, where it has been verified to pass with the `powerpc64le-linux-gnu', `riscv64-linux-gnu', and `vax-netbsdelf' targets. I'm fine to move it to the VAX part of the testsuite though if there's disagreement as to my choice. Otherwise OK to apply for this part? NB as a serious backend issue I mean to backport this change to active release branches as well. Maciej --- gcc/config/vax/vax.cc | 9 ++++++--- gcc/testsuite/gcc.dg/torture/pr111815.c | 26 ++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 3 deletions(-) gcc-vax-index-ashift-noncommutative.diff Index: gcc/gcc/config/vax/vax.cc =================================================================== --- gcc.orig/gcc/config/vax/vax.cc +++ gcc/gcc/config/vax/vax.cc @@ -1831,7 +1831,9 @@ nonindexed_address_p (rtx x, bool strict } /* True if PROD is either a reg times size of mode MODE and MODE is less - than or equal 8 bytes, or just a reg if MODE is one byte. */ + than or equal 8 bytes, or just a reg if MODE is one byte. For a MULT + RTX we accept its operands in either order, however ASHIFT is not + commutative, so in that case reg has to be the left operand. */ static bool index_term_p (rtx prod, machine_mode mode, bool strict) @@ -1850,8 +1852,9 @@ index_term_p (rtx prod, machine_mode mod xfoo0 = XEXP (prod, 0); xfoo1 = XEXP (prod, 1); - if (CONST_INT_P (xfoo0) - && GET_MODE_SIZE (mode) == (log_p ? 1 << INTVAL (xfoo0) : INTVAL (xfoo0)) + if (!log_p + && CONST_INT_P (xfoo0) + && GET_MODE_SIZE (mode) == INTVAL (xfoo0) && INDEX_REGISTER_P (xfoo1, strict)) return true; Index: gcc/gcc/testsuite/gcc.dg/torture/pr111815.c =================================================================== --- /dev/null +++ gcc/gcc/testsuite/gcc.dg/torture/pr111815.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ + +char x[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +__attribute__ ((noinline)) char * +p (char *a, int o, int i) +{ + return a + ++o + (1 << ++i); +} + +int +main (void) +{ + if (*p (x, 0, 0) != 3) + return 1; + if (*p (x, 1, 2) != 10) + return 1; + if (*p (x, 2, 1) != 7) + return 1; + if (*p (x, 3, 3) != 20) + return 1; + return 0; +}