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Wed, 14 Feb 2024 07:31:08 +0000 (GMT) Received: from smtpav03.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8F3205806A; Wed, 14 Feb 2024 07:31:07 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.179.40]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Wed, 14 Feb 2024 07:31:07 +0000 (GMT) Date: Wed, 14 Feb 2024 02:31:05 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: Patch [1 of 7]: Add initial -mcpu=future support. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4AKgA7m1gm7xUPk-ZtRrhDw80czXj-Fe X-Proofpoint-ORIG-GUID: M6qVgNIHs8R2idDsQ2P7FUNedCavqGEA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-13_16,2024-02-12_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402140057 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790858667555560290 X-GMAIL-MSGID: 1790858667555560290 This patch adds the basic support for -mcpu=future, which is a framework to add support for possible future PowerPCs. This patch is only sets the future bit in the ISA options. Can I check this into GCC 15 when it opens up, and immediately back port it to GCC 14 after GCC 14.0 is released? 2024-02-14 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option bits for -mcpu=future. (POWERPC_MASKS): Add -mfuture mask. (future cpu): Add -mcpu=future. * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor type. * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Likewise. * config/rs6000/rs6000.md (cpu attribute): Likewise. * config/rs6000/rs6000.opt (-mfuture): New insert mask for -mcpu=future. * doc/invoke.texi (PowerPC options): Add -mcpu=future. --- gcc/config/rs6000/rs6000-cpus.def | 6 ++++++ gcc/config/rs6000/rs6000-opts.h | 1 + gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 4 ++++ gcc/doc/invoke.texi | 2 +- 6 files changed, 16 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index d28cc87eb2a..a47075f8249 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -88,6 +88,10 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) +/* Flags for a potential future processor that may or may not be delivered. */ +#define ISA_FUTURE_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_FUTURE) + /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -135,6 +139,7 @@ | OPTION_MASK_LOAD_VECTOR_PAIR \ | OPTION_MASK_POWER10 \ | OPTION_MASK_P10_FUSION \ + | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ @@ -267,3 +272,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 33fd0efc936..b2ae180c0f0 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -62,6 +62,7 @@ enum processor_type PROCESSOR_POWER8, PROCESSOR_POWER9, PROCESSOR_POWER10, + PROCESSOR_FUTURE, PROCESSOR_RS64A, PROCESSOR_MPCCORE, diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 65f46709716..97fa98a2e65 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +EnumValue +Enum(rs6000_cpu_opt_value) String(future) Value(57) + diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4acb4031ae0..bd0ecdd9007 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -350,7 +350,7 @@ (define_attr "cpu" ppc750,ppc7400,ppc7450, ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, - power4,power5,power6,power7,power8,power9,power10, + power4,power5,power6,power7,power8,power9,power10,future, rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 60b923f5e4b..4ad1d8e302c 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -612,6 +612,10 @@ mrop-protect Target Var(rs6000_rop_protect) Init(0) Enable instructions that guard against return-oriented programming attacks. +mfuture +Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>) +Generate (do not generate) store vector pair instructions. + mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71339b8b30f..dcc9f82171c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31091,7 +31091,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, and @samp{native}. +@samp{powerpc64le}, @samp{rs64}, @samp{future}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either