From patchwork Fri Jan 5 22:18:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 185551 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:6f82:b0:100:9c79:88ff with SMTP id tb2csp6497295dyb; Fri, 5 Jan 2024 14:18:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHwNDQtUDHOyQ3rCsZ1rhE4gWNdOKrvXEGZowuqZnjPpBBG5t9syKXgSVFgJBaeod3Ivu7D X-Received: by 2002:a05:6214:c49:b0:680:53c:5e5a with SMTP id r9-20020a0562140c4900b00680053c5e5amr39988qvj.114.1704493137871; Fri, 05 Jan 2024 14:18:57 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1704493137; cv=pass; d=google.com; s=arc-20160816; b=j3TQb1j/EwmXoTGHVC1DY1RVIMuATcURUcJUzjG1FHOnHprVHN20yK6jASpzGKzvpA 1sxOmigr9jtnjlWJjeDT7SHsWJka30ujdxz8TZK7hNqtub21pUfU3UnjZ5NmlZGjH8VY cZLwHMgg4c9eKGjv+gSxTFg8UG311rm8BMCoMdP4LDjNjjdFrO9ju956uM14cjIdgoAM vEA5lcOi0ntOwaL/kBM28ZL3EFcxM05xJxV33Saoh2og5077ydDKcFO0c2gRsvLZxlU0 jy35XYmlmwrSGVHF6mW2fQNeN9fc1ogJeBJ7sOt2qepHn/iyLQvnzGRBp8dPDv+GmTcw 0hqg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-disposition :mime-version:mail-followup-to:message-id:subject:to:from:date :dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=4Ikw2sA953zD3r3lrT/D8Nb2WKCq5KghY14tc478+bQ=; fh=0bQqz0x7CUT8I+BDaNEJSevw0DVHT666RDr0Mh+m1Jk=; b=dTmtWcmmYpDfk2KBQmTwTD8s0Vn05YswuS7ugyKkEuJxlUx0e6o7f03cSp3tI76RSu CkKkqiJcqHFmFWb5zQRRhz3lC+3O3TvQQLjiZ1tyfY9YDucj/Y7WzklMLn96mX0VmbBD 3o/ZwcQppBBjAXN2i/FOE+liweUPt8z563cQbnh6OOy95n7KDG+twa0K9vXzmcBqyPFn KjsLnSp24DwKdG8sfYYvO9KPzpA3XC4ubDOqaqkFFfqX6kas4wpl3y7lLNeYnQjR9vko 71fepnJBZKnzcnpnH5413artWdNyfTqO/OobFj/08DHoJmo9NVPmU0HuoATSCeWGPX4d 7+Cw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=K5YzGtXM; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v6-20020a0cdd86000000b0068091ad8367si2628878qvk.406.2024.01.05.14.18.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jan 2024 14:18:57 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=K5YzGtXM; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8F3D9385E44F for ; Fri, 5 Jan 2024 22:18:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 34FA73857B8B for ; Fri, 5 Jan 2024 22:18:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 34FA73857B8B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 34FA73857B8B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704493095; cv=none; b=NN0A+5NJ9ntYK5XAS07Je8GyITlRWxcbA+VKr/J4xa8Idu5zG2gIODzs8ykkr4Vgsthhl5eL8T3w3tBtBhBWe4cMe1JbDwj3vJ7ro6IruSpa2QdUF8KbGt77Fh1atciD+SIbwDeUuXL6Of7/czHWRvSeh5//ksgA4/bjR1bCPiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704493095; c=relaxed/simple; bh=4YDNFOday9Qh3yBljR7i8vP88dgdpHAlN3jMfx7OPcc=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=ti0TCEOLSFuFQLP+dx8Q5vDOa3Uabqg8O1H8V60XptNx5FgvOOWdMPqZ4AbBEr/Pc2qdhl0oOZOXov1vJ4dc6jxUZrcSS0j/O7QbYM/ACrb2W6D4O9u+aEDTdI2itiHyi7LP9p5txE1Kb8TmOXB6omOPvckUaCEKJjJiL0jIPHY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 405LPeHJ013501; Fri, 5 Jan 2024 22:18:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=date : from : to : subject : message-id : mime-version : content-type; s=pp1; bh=4Ikw2sA953zD3r3lrT/D8Nb2WKCq5KghY14tc478+bQ=; b=K5YzGtXMHG1aH6YJv07uOpMMi9I1lCr0T90gdpyG5LLHNzvO2fPbQTTzyJWL9rlWLhsS obR/XTcCAbw7aN+AMSZwK07xhSY4BNs0ReXROSwo6RHeVG5ERKOkDeU6E7XRsnsMIAwY jT5MGrWI8cV7CeQ7kpNNQscK/IMuOsf1S9KLpskFGBEDaq0l6isPX/6dYeWZt5Ek7F5e wBTnacJsEoJ2niLisCvdcDav2C4GktGxGDIVAVxMpeQRCtx5Sr910KwD3E30zCLQcD7P lXwC5IqnilarEvt0X4ZerS0Kh9Pf/AzNU2xGSqy+e0vuaG2PXSoaKc94I6eK3ZN7PtgN Nw== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3vervx9w1e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Jan 2024 22:18:11 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 405MIBH3025449; Fri, 5 Jan 2024 22:18:11 GMT Received: from ppma21.wdc07v.mail.ibm.com (5b.69.3da9.ip4.static.sl-reverse.com [169.61.105.91]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3vervx9w12-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Jan 2024 22:18:11 +0000 Received: from pps.filterd (ppma21.wdc07v.mail.ibm.com [127.0.0.1]) by ppma21.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 405JiMUB007000; Fri, 5 Jan 2024 22:18:09 GMT Received: from smtprelay04.wdc07v.mail.ibm.com ([172.16.1.71]) by ppma21.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3vaxhpj865-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Jan 2024 22:18:09 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 405MI8ZK50069822 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 5 Jan 2024 22:18:09 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AC0FA5805D; Fri, 5 Jan 2024 22:18:08 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4426758056; Fri, 5 Jan 2024 22:18:08 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.128.150]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTPS; Fri, 5 Jan 2024 22:18:08 +0000 (GMT) Date: Fri, 5 Jan 2024 17:18:06 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: [PATCH] PR target/112886, Add %S to print_operand for vector pair support Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner MIME-Version: 1.0 Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: RGH6rGg6UrGME53lmPUUAERDp3g0aMhc X-Proofpoint-GUID: Mox9QPswa8X1vSW7TcnGU0ptjjfsVM1A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=940 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401050173 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787290596288871392 X-GMAIL-MSGID: 1787290596288871392 In looking at support for load vector pair and store vector pair for the PowerPC in GCC, I noticed that we were missing a print_operand output modifier if you are dealing with vector pairs to print the 2nd register in the vector pair. If the instruction inside of the asm used the Altivec encoding, then we could use the %L modifier: __vector_pair *p, *q, *r; // ... __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2" : "=v" (*p) : "v" (*q), "v" (*r)); Likewise if we know the value to be in a tradiational FPR register, %L will work for instructions that use the VSX encoding: __vector_pair *p, *q, *r; // ... __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2" : "=f" (*p) : "f" (*q), "f" (*r)); But if have a value that is in a traditional Altivec register, and the instruction uses the VSX encoding, %L will a value between 0 and 31, when it should give a value between 32 and 63. This patch adds %S that acts like %x, except that it adds 1 to the register number. I have tested this on power10 and power9 little endian systems and on a power9 big endian system. There were no regressions in the patch. Can I apply it to the trunk? It would be nice if I could apply it to the open branches. Can I backport it after a burn-in period? 2024-01-04 Michael Meissner gcc/ PR target/112886 * config/rs6000/rs6000.cc (print_operand): Add %S output modifier. * doc/md.texi (Modifiers): Mention %S can be used like %x. gcc/testsuite/ PR target/112886 * /gcc.target/powerpc/pr112886.c: New test. --- gcc/config/rs6000/rs6000.cc | 10 +++++++--- gcc/doc/md.texi | 5 +++-- gcc/testsuite/gcc.target/powerpc/pr112886.c | 19 +++++++++++++++++++ 3 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr112886.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 5a7e00b03d1..ba89377c9ec 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -14504,13 +14504,17 @@ print_operand (FILE *file, rtx x, int code) print_operand (file, x, 0); return; + case 'S': case 'x': - /* X is a FPR or Altivec register used in a VSX context. */ + /* X is a FPR or Altivec register used in a VSX context. %x prints + the VSX register number, %S prints the 2nd register number for + vector pair, decimal 128-bit floating and IBM 128-bit binary floating + values. */ if (!REG_P (x) || !VSX_REGNO_P (REGNO (x))) - output_operand_lossage ("invalid %%x value"); + output_operand_lossage ("invalid %%%c value", (code == 'S' ? 'S' : 'x')); else { - int reg = REGNO (x); + int reg = REGNO (x) + (code == 'S' ? 1 : 0); int vsx_reg = (FP_REGNO_P (reg) ? reg - 32 : reg - FIRST_ALTIVEC_REGNO + 32); diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 47a87d6ceec..53ec957cb23 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3386,8 +3386,9 @@ A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}). -When using @code{wa}, you should use the @code{%x} output modifier, so that -the correct register number is printed. For example: +When using @code{wa}, you should use either the @code{%x} or @code{%S} +output modifier, so that the correct register number is printed. For +example: @smallexample asm ("xvadddp %x0,%x1,%x2" diff --git a/gcc/testsuite/gcc.target/powerpc/pr112886.c b/gcc/testsuite/gcc.target/powerpc/pr112886.c new file mode 100644 index 00000000000..07196bdc220 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr112886.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* PR target/112886: Test that print_operand %S gives the correct register + number for VSX registers (i.e. if the register is an Altivec register, the + register number is 32..63 instead of 0..31. */ + +void +test (__vector_pair *p, __vector_pair *q, __vector_pair *r) +{ + __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %S0,%S1,%S2" + : "=v" (*p) + : "v" (*q), "v" (*r)); +} + +/* { dg-final { scan-assembler-times {\mxvadddp (3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3]),(3[2-9]|[45][0-9]|6[0-3])\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 1 } } */