diff mbox series

Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL

Message ID	ZRcSyEgIA15zhiQy@cowardly-lion.the-meissners.org
State	Accepted
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8B3B33858D32 Date: Fri, 29 Sep 2023 14:09:12 -0400 From: Michael Meissner <meissner@linux.ibm.com> To: gcc-patches@gcc.gnu.org, Michael Meissner <meissner@linux.ibm.com>, Segher Boessenkool <segher@kernel.crashing.org>, "Kewen.Lin" <linkw@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, Peter Bergner <bergner@linux.ibm.com> Subject: [PATCH] Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL Message-ID: <ZRcSyEgIA15zhiQy@cowardly-lion.the-meissners.org> Mail-Followup-To: Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org, Segher Boessenkool <segher@kernel.crashing.org>, "Kewen.Lin" <linkw@linux.ibm.com>, David Edelsohn <dje.gcc@gmail.com>, Peter Bergner <bergner@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX
Series	Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL \| Cleanup: Replace UNSPEC_COPYSIGN with copysign RTL

Checks

Context	Check	Description
snail/gcc-patch-check	success	Github commit url

Commit Message

Michael Meissner Sept. 29, 2023, 6:09 p.m. UTC

  When I first implemented COPYSIGN support in the power7 days, we did not have a
copysign RTL insn, so I had to use UNSPEC to represent the copysign
instruction.  This patch removes those UNSPECs, and it uses the native RTL
copysign insn.

I have tested this on both big endian and little endian PowerPC server systems,
and there were no regressions.  Can I check this into the master branch?  Since
it is just a clean-up, I don't see the need to back port it, but it is simple
to do the back port if desired.

2023-09-29  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
	(copysign<mode>3_fcpsg): Use copysign RTL instead of UNSPEC.
	(copysign<mode>3_hard): Likewise.
	(copysign<mode>3_soft): Likewise.
	* config/rs6000/vector.md (vector_copysign<mode>3): Use copysign RTL
	instead of UNSPEC.
	* config/rs6000/vsx.md (vsx_copysign<mode>3): Use copysign RTL instead
	of UNSPEC.
---
 gcc/config/rs6000/rs6000.md | 20 ++++++++------------
 gcc/config/rs6000/vector.md |  4 ++--
 gcc/config/rs6000/vsx.md    |  7 +++----
 3 files changed, 13 insertions(+), 18 deletions(-)

Comments

David Edelsohn Sept. 29, 2023, 7:44 p.m. UTC | #1

On Fri, Sep 29, 2023 at 2:09 PM Michael Meissner <meissner@linux.ibm.com>
wrote:

> When I first implemented COPYSIGN support in the power7 days, we did not
> have a
> copysign RTL insn, so I had to use UNSPEC to represent the copysign
> instruction.  This patch removes those UNSPECs, and it uses the native RTL
> copysign insn.
>
> I have tested this on both big endian and little endian PowerPC server
> systems,
> and there were no regressions.  Can I check this into the master branch?
> Since
> it is just a clean-up, I don't see the need to back port it, but it is
> simple
> to do the back port if desired.
>
> 2023-09-29  Michael Meissner  <meissner@linux.ibm.com>
>
> gcc/
>
>         * config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
>         (copysign<mode>3_fcpsg): Use copysign RTL instead of UNSPEC.
>         (copysign<mode>3_hard): Likewise.
>         (copysign<mode>3_soft): Likewise.
>         * config/rs6000/vector.md (vector_copysign<mode>3): Use copysign
> RTL
>         instead of UNSPEC.
>         * config/rs6000/vsx.md (vsx_copysign<mode>3): Use copysign RTL
> instead
>         of UNSPEC.
> ---
>  gcc/config/rs6000/rs6000.md | 20 ++++++++------------
>  gcc/config/rs6000/vector.md |  4 ++--
>  gcc/config/rs6000/vsx.md    |  7 +++----
>  3 files changed, 13 insertions(+), 18 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 7b583d7a69a..1b6b6cb5bbe 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -108,7 +108,6 @@ (define_c_enum "unspec"
>     UNSPEC_TOCREL
>     UNSPEC_MACHOPIC_OFFSET
>     UNSPEC_BPERM
> -   UNSPEC_COPYSIGN
>     UNSPEC_PARITY
>     UNSPEC_CMPB
>     UNSPEC_FCTIW
> @@ -5383,9 +5382,8 @@ (define_expand "copysign<mode>3"
>  ;; compiler from optimizing -0.0
>

The comment above the define_insn refers to UNSPEC instead of if-then-else
because of -0.0.
Please remove or update the comment because the pattern no longer uses
UNSPEC.

The rest of the patch is okay with that change.

Thanks, David


>  (define_insn "copysign<mode>3_fcpsgn"
>    [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
> -       (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
> -                     (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
> -                    UNSPEC_COPYSIGN))]
> +       (copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
> +                      (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
>    "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
>    "@
>     fcpsgn %0,%2,%1
> @@ -14984,10 +14982,9 @@ (define_expand "copysign<mode>3"
>
>  (define_insn "copysign<mode>3_hard"
>    [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> -       (unspec:IEEE128
> -        [(match_operand:IEEE128 1 "altivec_register_operand" "v")
> -         (match_operand:IEEE128 2 "altivec_register_operand" "v")]
> -        UNSPEC_COPYSIGN))]
> +       (copysign:IEEE128
> +        (match_operand:IEEE128 1 "altivec_register_operand" "v")
> +        (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
>    "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
>     "xscpsgnqp %0,%2,%1"
>    [(set_attr "type" "vecmove")
> @@ -14995,10 +14992,9 @@ (define_insn "copysign<mode>3_hard"
>
>  (define_insn "copysign<mode>3_soft"
>    [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> -       (unspec:IEEE128
> -        [(match_operand:IEEE128 1 "altivec_register_operand" "v")
> -         (match_operand:IEEE128 2 "altivec_register_operand" "v")]
> -        UNSPEC_COPYSIGN))
> +       (copysign:IEEE128
> +        (match_operand:IEEE128 1 "altivec_register_operand" "v")
> +        (match_operand:IEEE128 2 "altivec_register_operand" "v")))
>     (clobber (match_scratch:IEEE128 3 "=&v"))]
>    "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
>     "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
> diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
> index 1ae04c8e0a8..f4fc620b653 100644
> --- a/gcc/config/rs6000/vector.md
> +++ b/gcc/config/rs6000/vector.md
> @@ -332,8 +332,8 @@ (define_expand "vector_btrunc<mode>2"
>
>  (define_expand "vector_copysign<mode>3"
>    [(set (match_operand:VEC_F 0 "vfloat_operand")
> -       (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
> -                      (match_operand:VEC_F 2 "vfloat_operand")]
> UNSPEC_COPYSIGN))]
> +       (copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
> +                       (match_operand:VEC_F 2 "vfloat_operand")))]
>    "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
>  {
>    if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 4de41e78d51..f3b40229094 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -2233,10 +2233,9 @@ (define_insn "*vsx_ge_<mode>_p"
>  ;; Copy sign
>  (define_insn "vsx_copysign<mode>3"
>    [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
> -       (unspec:VSX_F
> -        [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
> -         (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
> -        UNSPEC_COPYSIGN))]
> +       (copysign:VSX_F
> +        (match_operand:VSX_F 1 "vsx_register_operand" "wa")
> +        (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
>    "VECTOR_UNIT_VSX_P (<MODE>mode)"
>    "xvcpsgn<sd>p %x0,%x2,%x1"
>    [(set_attr "type" "<VStype_simple>")])
> --
> 2.41.0
>
>
> --
> Michael Meissner, IBM
> PO Box 98, Ayer, Massachusetts, USA, 01432
> email: meissner@linux.ibm.com
>

Segher Boessenkool Oct. 1, 2023, 12:32 a.m. UTC | #2

On Fri, Sep 29, 2023 at 02:09:12PM -0400, Michael Meissner wrote:
> 	* config/rs6000/rs6000.md (UNSPEC_COPYSIGN): Delete.
> 	(copysign<mode>3_fcpsg): Use copysign RTL instead of UNSPEC.

(typo, it is _fcpsgn)

Nice to see unnecessary unspecs going away :-)


Segher

diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7b583d7a69a..1b6b6cb5bbe 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -108,7 +108,6 @@  (define_c_enum "unspec"
    UNSPEC_TOCREL
    UNSPEC_MACHOPIC_OFFSET
    UNSPEC_BPERM
-   UNSPEC_COPYSIGN
    UNSPEC_PARITY
    UNSPEC_CMPB
    UNSPEC_FCTIW
@@ -5383,9 +5382,8 @@  (define_expand "copysign<mode>3"
 ;; compiler from optimizing -0.0
 (define_insn "copysign<mode>3_fcpsgn"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
-	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
-		      (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")]
-		     UNSPEC_COPYSIGN))]
+	(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") 
+		       (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
   "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
   "@
    fcpsgn %0,%2,%1
@@ -14984,10 +14982,9 @@  (define_expand "copysign<mode>3"
 
 (define_insn "copysign<mode>3_hard"
   [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
-	(unspec:IEEE128
-	 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
-	  (match_operand:IEEE128 2 "altivec_register_operand" "v")]
-	 UNSPEC_COPYSIGN))]
+	(copysign:IEEE128
+	 (match_operand:IEEE128 1 "altivec_register_operand" "v")
+	 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
   "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
    "xscpsgnqp %0,%2,%1"
   [(set_attr "type" "vecmove")
@@ -14995,10 +14992,9 @@  (define_insn "copysign<mode>3_hard"
 
 (define_insn "copysign<mode>3_soft"
   [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
-	(unspec:IEEE128
-	 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
-	  (match_operand:IEEE128 2 "altivec_register_operand" "v")]
-	 UNSPEC_COPYSIGN))
+	(copysign:IEEE128
+	 (match_operand:IEEE128 1 "altivec_register_operand" "v")
+	 (match_operand:IEEE128 2 "altivec_register_operand" "v")))
    (clobber (match_scratch:IEEE128 3 "=&v"))]
   "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
    "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 1ae04c8e0a8..f4fc620b653 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -332,8 +332,8 @@  (define_expand "vector_btrunc<mode>2"
 
 (define_expand "vector_copysign<mode>3"
   [(set (match_operand:VEC_F 0 "vfloat_operand")
-	(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
-		       (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))]
+	(copysign:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
+			(match_operand:VEC_F 2 "vfloat_operand")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
 {
   if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4de41e78d51..f3b40229094 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2233,10 +2233,9 @@  (define_insn "*vsx_ge_<mode>_p"
 ;; Copy sign
 (define_insn "vsx_copysign<mode>3"
   [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
-	(unspec:VSX_F
-	 [(match_operand:VSX_F 1 "vsx_register_operand" "wa")
-	  (match_operand:VSX_F 2 "vsx_register_operand" "wa")]
-	 UNSPEC_COPYSIGN))]
+	(copysign:VSX_F
+	 (match_operand:VSX_F 1 "vsx_register_operand" "wa")
+	 (match_operand:VSX_F 2 "vsx_register_operand" "wa")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "xvcpsgn<sd>p %x0,%x2,%x1"
   [(set_attr "type" "<VStype_simple>")])