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[8.43.85.97]) by mx.google.com with ESMTPS id u18-20020a1709060b1200b00977e918e260si10773266ejg.618.2023.07.15.10.39.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jul 2023 10:39:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1A0E43858430 for ; Sat, 15 Jul 2023 17:39:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dellerweb.de (dellerweb.de [173.249.48.176]) by sourceware.org (Postfix) with ESMTPS id 458093858D35 for ; Sat, 15 Jul 2023 17:39:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 458093858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=parisc-linux.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=parisc-linux.org Received: from mx3210.localdomain (unknown [142.181.186.176]) by dellerweb.de (Postfix) with ESMTPSA id 319501600085 for ; Sat, 15 Jul 2023 19:39:17 +0200 (CEST) Received: by mx3210.localdomain (Postfix, from userid 1000) id C3E5322012C; Sat, 15 Jul 2023 17:39:15 +0000 (UTC) Date: Sat, 15 Jul 2023 17:39:15 +0000 From: John David Anglin To: GCC Patches Subject: [committed] hppa: Modify TLS patterns to provide both 32 and 64-bit support Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771509168647997352 X-GMAIL-MSGID: 1771509168647997352 Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11. Committed to trunk. Dave --- hppa: Modify TLS patterns to provide both 32 and 64-bit support. 2023-07-15 John David Anglin gcc/ChangeLog: * config/pa/pa.md: Define constants R1_REGNUM, R19_REGNUM and R27_REGNUM. (tgd_load): Restrict to !TARGET_64BIT. Use register constants. (tld_load): Likewise. (tgd_load_pic): Change to expander. (tld_load_pic, tld_offset_load, tp_load): Likewise. (tie_load_pic, tle_load): Likewise. (tgd_load_picsi, tgd_load_picdi): New. (tld_load_picsi, tld_load_picdi): New. (tld_offset_load): New. (tp_load): New. (tie_load_picsi, tie_load_picdi): New. (tle_load): New. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 726e12768f8..f603591447d 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -108,6 +108,14 @@ (MAX_17BIT_OFFSET 262100) ; 17-bit branch ]) +;; Register numbers + +(define_constants + [(R1_REGNUM 1) + (R19_REGNUM 19) + (R27_REGNUM 27) + ]) + ;; Mode and code iterators ;; This mode iterator allows :P to be used for patterns that operate on @@ -10262,9 +10270,9 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (define_insn "tgd_load" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD)) - (clobber (reg:SI 1)) - (use (reg:SI 27))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R27_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\"; @@ -10272,12 +10280,25 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tgd_load_pic" +(define_expand "tgd_load_pic" + [(set (match_operand 0 "register_operand") + (unspec [(match_operand 1 "tgd_symbolic_operand")] UNSPEC_TLSGD_PIC)) + (clobber (reg R1_REGNUM))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tgd_load_picdi (operands[0], operands[1])); + else + emit_insn (gen_tgd_load_picsi (operands[0], operands[1])); + DONE; +}) + +(define_insn "tgd_load_picsi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC)) - (clobber (reg:SI 1)) - (use (reg:SI 19))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R19_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\"; @@ -10285,12 +10306,25 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) +(define_insn "tgd_load_picdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC)) + (clobber (reg:DI R1_REGNUM)) + (use (reg:DI R27_REGNUM))] + "TARGET_64BIT" + "* +{ + return \"addil LT'%1-$tls_gdidx$,%%r27\;ldo RT'%1-$tls_gdidx$(%%r1),%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + (define_insn "tld_load" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM)) - (clobber (reg:SI 1)) - (use (reg:SI 27))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R27_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\"; @@ -10298,12 +10332,25 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tld_load_pic" +(define_expand "tld_load_pic" + [(set (match_operand 0 "register_operand") + (unspec [(match_operand 1 "tld_symbolic_operand")] UNSPEC_TLSLDM_PIC)) + (clobber (reg R1_REGNUM))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tld_load_picdi (operands[0], operands[1])); + else + emit_insn (gen_tld_load_picsi (operands[0], operands[1])); + DONE; +}) + +(define_insn "tld_load_picsi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC)) - (clobber (reg:SI 1)) - (use (reg:SI 19))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R19_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\"; @@ -10311,12 +10358,40 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tld_offset_load" - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] +(define_insn "tld_load_picdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC)) + (clobber (reg:DI R1_REGNUM)) + (use (reg:DI R27_REGNUM))] + "TARGET_64BIT" + "* +{ + return \"addil LT'%1-$tls_ldidx$,%%r27\;ldo RT'%1-$tls_ldidx$(%%r1),%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + +(define_expand "tld_offset_load" + [(set (match_operand 0 "register_operand") + (plus (unspec [(match_operand 1 "tld_symbolic_operand")] UNSPEC_TLSLDO) - (match_operand:SI 2 "register_operand" "r"))) - (clobber (reg:SI 1))] + (match_operand 2 "register_operand"))) + (clobber (reg R1_REGNUM))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tld_offset_loaddi (operands[0], operands[1], operands[2])); + else + emit_insn (gen_tld_offset_loadsi (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_insn "tld_offset_load" + [(set (match_operand:P 0 "register_operand" "=r") + (plus:P (unspec:P [(match_operand 1 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:P 2 "register_operand" "r"))) + (clobber (reg:P R1_REGNUM))] "" "* { @@ -10325,9 +10400,21 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tp_load" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_TP))] +(define_expand "tp_load" + [(set (match_operand 0 "register_operand") + (unspec [(const_int 0)] UNSPEC_TP))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tp_loaddi (operands[0])); + else + emit_insn (gen_tp_loadsi (operands[0])); + DONE; +}) + +(define_insn "tp_load" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(const_int 0)] UNSPEC_TP))] "" "mfctl %%cr27,%0" [(set_attr "type" "multi") @@ -10336,9 +10423,9 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (define_insn "tie_load" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE)) - (clobber (reg:SI 1)) - (use (reg:SI 27))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R27_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\"; @@ -10346,12 +10433,25 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tie_load_pic" +(define_expand "tie_load_pic" + [(set (match_operand 0 "register_operand") + (unspec [(match_operand 1 "tie_symbolic_operand")] UNSPEC_TLSIE_PIC)) + (clobber (reg R1_REGNUM))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tie_load_picdi (operands[0], operands[1])); + else + emit_insn (gen_tie_load_picsi (operands[0], operands[1])); + DONE; +}) + +(define_insn "tie_load_picsi" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC)) - (clobber (reg:SI 1)) - (use (reg:SI 19))] - "" + (clobber (reg:SI R1_REGNUM)) + (use (reg:SI R19_REGNUM))] + "!TARGET_64BIT" "* { return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\"; @@ -10359,12 +10459,40 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "multi") (set_attr "length" "8")]) -(define_insn "tle_load" - [(set (match_operand:SI 0 "register_operand" "=r") - (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")] +(define_insn "tie_load_picdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC)) + (clobber (reg:DI R1_REGNUM)) + (use (reg:DI R27_REGNUM))] + "!TARGET_64BIT" + "* +{ + return \"addil LT'%1-$tls_ieoff$,%%r27\;ldd RT'%1-$tls_ieoff$(%%r1),%0\"; +}" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + +(define_expand "tle_load" + [(set (match_operand 0 "register_operand") + (plus (unspec [(match_operand 1 "tle_symbolic_operand")] UNSPEC_TLSLE) - (match_operand:SI 2 "register_operand" "r"))) - (clobber (reg:SI 1))] + (match_operand 2 "register_operand"))) + (clobber (reg R1_REGNUM))] + "" +{ + if (TARGET_64BIT) + emit_insn (gen_tle_loaddi (operands[0], operands[1], operands[2])); + else + emit_insn (gen_tle_loadsi (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_insn "tle_load" + [(set (match_operand:P 0 "register_operand" "=r") + (plus:P (unspec:P [(match_operand 1 "tle_symbolic_operand" "")] + UNSPEC_TLSLE) + (match_operand:P 2 "register_operand" "r"))) + (clobber (reg:P R1_REGNUM))] "" "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0" [(set_attr "type" "multi")