diff mbox series

[committed] i386: Fix up mode iterators that weren't expanded [PR106721]

Message ID YwXbm/bBL5VdJ4n/@tucnak
State New, archived
Headers
Series [committed] i386: Fix up mode iterators that weren't expanded [PR106721] |

Commit Message

Jakub Jelinek Aug. 24, 2022, 8:04 a.m. UTC 
  Hi!

Currently, when md file reader sees <something> and something is valid mode
(or code) attribute but which doesn't include case for the current mode
(or code), it just keeps the <something> untouched.
I went through all cases matching <[a-zA-Z] in tmp-mddump.md after make mddump.
Most of the cases were related to the recent V*BF mode additions, some
to V*HF mode too, and there was one typo.

Bootstrapped/regtested on x86_64-linux and i686-linux, preapproved in
bugzilla with the request to use i instead of f for V*[BH]F (similarly
to V*HI mode).

2022-08-24  Jakub Jelinek  <jakub@redhat.com>

	PR target/106721
	* config/i386/sse.md (shuffletype): Add V32BF, V16BF and V8BF entries.
	Change V32HF, V16HF and V8HF entries from "f" to "i".
	(iptr): Add V32BF, V16BF, V8BF and BF entries.
	(i128vldq): Add V16HF and V16BF entries.
	(avx512er_vmrcp28<mode><mask_name><round_saeonly_name>): Fix typo,
	mask_opernad3 -> mask_operand3.

	* gcc.target/i386/avx512vl-pr106721.c: New test.


	Jakub
diff mbox series

Patch

--- gcc/config/i386/sse.md.jj	2022-08-19 16:00:05.042390249 +0200
+++ gcc/config/i386/sse.md	2022-08-24 09:40:50.159956792 +0200
@@ -747,7 +747,8 @@ 
    (V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw")])
 
 (define_mode_attr shuffletype
-  [(V32HF "f") (V16HF "f") (V8HF "f")
+  [(V32HF "i") (V16HF "i") (V8HF "i")
+   (V32BF "i") (V16BF "i") (V8BF "i")
    (V16SF "f") (V16SI "i") (V8DF "f") (V8DI "i")
    (V8SF "f") (V8SI "i") (V4DF "f") (V4DI "i")
    (V4SF "f") (V4SI "i") (V2DF "f") (V2DI "i")
@@ -1136,10 +1137,10 @@ 
   [(V64QI "b") (V32HI "w") (V16SI "k") (V8DI "q")
    (V32QI "b") (V16HI "w") (V8SI "k") (V4DI "q")
    (V16QI "b") (V8HI "w") (V4SI "k") (V2DI "q")
-   (V32HF "w") (V16SF "k") (V8DF "q")
-   (V16HF "w") (V8SF "k") (V4DF "q")
-   (V8HF "w") (V4SF "k") (V2DF "q")
-   (HF "w") (SF "k") (DF "q")])
+   (V32HF "w") (V32BF "w") (V16SF "k") (V8DF "q")
+   (V16HF "w") (V16BF "w") (V8SF "k") (V4DF "q")
+   (V8HF "w") (V8BF "w") (V4SF "k") (V2DF "q")
+   (HF "w") (BF "w") (SF "k") (DF "q")])
 
 ;; Mapping of vector modes to VPTERNLOG suffix
 (define_mode_attr ternlogsuffix
@@ -1251,7 +1252,7 @@ 
 ;; For 256-bit modes for TARGET_AVX512VL && TARGET_AVX512DQ
 ;; i32x4, f32x4, i64x2 or f64x2 suffixes.
 (define_mode_attr i128vldq
-  [(V8SF "f32x4") (V4DF "f64x2")
+  [(V16HF "i32x4") (V16BF "i32x4") (V8SF "f32x4") (V4DF "f64x2")
    (V32QI "i32x4") (V16HI "i32x4") (V8SI "i32x4") (V4DI "i64x2")])
 
 ;; Mix-n-match
@@ -23897,7 +23898,7 @@ 
 	  (match_operand:VF_128 2 "register_operand" "v")
 	  (const_int 1)))]
   "TARGET_AVX512ER"
-  "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_mask_op3>%1, %2, %0<mask_operand3>|<mask_opernad3>%0, %2, %<iptr>1<round_saeonly_mask_op3>}"
+  "vrcp28<ssescalarmodesuffix>\t{<round_saeonly_mask_op3>%1, %2, %0<mask_operand3>|<mask_operand3>%0, %2, %<iptr>1<round_saeonly_mask_op3>}"
   [(set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
    (set_attr "type" "sse")
--- gcc/testsuite/gcc.target/i386/avx512vl-pr106721.c.jj	2022-08-23 13:31:57.590639970 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-pr106721.c	2022-08-23 13:31:31.271994165 +0200
@@ -0,0 +1,19 @@ 
+/* PR target/106721 */
+/* { dg-do assemble { target avx512vl } } */
+/* { dg-options "-O3 -mavx512vl" } */
+
+typedef __bf16 __m256bf16 __attribute__((__vector_size__(32)));
+void (*bar) (__m256bf16, __m256bf16, __m256bf16);
+__m256bf16 a;
+volatile __bf16 b, c, d, e, f, g, h;
+
+void
+foo (void)
+{
+  __m256bf16 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m256bf16) { b, c, d, e, f, g, h };
+  a = x[6];
+  bar (x[0], x[6], x[7]);
+}