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Thu, 18 Aug 2022 21:41:17 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 196F1BE04F; Thu, 18 Aug 2022 21:41:17 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A38ABE054; Thu, 18 Aug 2022 21:41:16 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.225.181]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 18 Aug 2022 21:41:16 +0000 (GMT) Date: Thu, 18 Aug 2022 17:41:14 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 2/3] Allow __ibm128 with -msoft-float (PR target/105334) Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4MoNhgTdvjujYMJW4jj13n9ShELEgkQZ X-Proofpoint-ORIG-GUID: aNUzID6dLoXj1bcqRdhzdoBCfaHTq5S9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 mlxlogscore=884 lowpriorityscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180077 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741536807399070891?= X-GMAIL-MSGID: =?utf-8?q?1741536807399070891?= Allow __ibm128 with -msoft-float (PR target/105334) This patch allows __ibm128 to be used on systems with software floating point enabled. Previously, we required hardware floating point to be enabled to use __ibm128 keyword and the __ibm128 built-in functions. This patch fixes PR target/105334. I have tested this patch on the following systems: 1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee 2) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm 3) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm 4) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm 5) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm 6) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm 7) BE Power8 using --with-cpu=power5 --with-long-double-format=ibm There were no regressions in the build or in the tests. On the power10 with long double using the IEEE 128-bit format, pr105334.c now runs where it previously failed. Can I check this patch into the trunk? Did we want to backport this to earlier GCC releases? 2022-08-17 Michael Meissner gcc/ PR target/105334 * config/rs6000/rs6000.cc (init_float128_ibm): Do not require hardware floating point for the IBM 128-bit floating point comparison functions. * config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not require hardware floating point to enable recognizing IBM 128-bit floating point modes. --- gcc/config/rs6000/rs6000.cc | 37 +++++++++++++++++-------------------- gcc/config/rs6000/rs6000.h | 2 +- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 39527ce9bbc..a6ec4c71ac0 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10913,26 +10913,23 @@ init_float128_ibm (machine_mode mode) set_optab_libfunc (smul_optab, mode, "__gcc_qmul"); set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv"); - if (!TARGET_HARD_FLOAT) - { - set_optab_libfunc (neg_optab, mode, "__gcc_qneg"); - set_optab_libfunc (eq_optab, mode, "__gcc_qeq"); - set_optab_libfunc (ne_optab, mode, "__gcc_qne"); - set_optab_libfunc (gt_optab, mode, "__gcc_qgt"); - set_optab_libfunc (ge_optab, mode, "__gcc_qge"); - set_optab_libfunc (lt_optab, mode, "__gcc_qlt"); - set_optab_libfunc (le_optab, mode, "__gcc_qle"); - set_optab_libfunc (unord_optab, mode, "__gcc_qunord"); - - set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq"); - set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq"); - set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos"); - set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod"); - set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi"); - set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou"); - set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq"); - set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq"); - } + set_optab_libfunc (neg_optab, mode, "__gcc_qneg"); + set_optab_libfunc (eq_optab, mode, "__gcc_qeq"); + set_optab_libfunc (ne_optab, mode, "__gcc_qne"); + set_optab_libfunc (gt_optab, mode, "__gcc_qgt"); + set_optab_libfunc (ge_optab, mode, "__gcc_qge"); + set_optab_libfunc (lt_optab, mode, "__gcc_qlt"); + set_optab_libfunc (le_optab, mode, "__gcc_qle"); + set_optab_libfunc (unord_optab, mode, "__gcc_qunord"); + + set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq"); + set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq"); + set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos"); + set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod"); + set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi"); + set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou"); + set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq"); + set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq"); } else { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 813ec696c0d..f58f5f3f355 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -337,7 +337,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define FLOAT128_IBM_P(MODE) \ ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ && ((MODE) == TFmode || (MODE) == TCmode)) \ - || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) + || ((MODE) == IFmode || (MODE) == ICmode)) /* Helper macros to say whether a 128-bit floating point type can go in a single vector register, or whether it needs paired scalar values. */