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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id du17-20020a17090772d100b007341ad4b028si20194626ejc.642.2022.10.21.00.16.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 00:16:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Uby4z/1E"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F28FF3857343 for ; Fri, 21 Oct 2022 07:16:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F28FF3857343 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666336582; bh=dP7B7nuKqbZ1JVADyYG1kwiQrpsZ95KxtVG8F3HLlfE=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=Uby4z/1EZiM9z7cyjZl8jza9eiY7YqZ+okiYj/qlHKWwzuL5cgVcifsjT64l9nrCD jR+FPEteQWmbfe/iGyGIAPJgjDBvnxOL+EU8cR8XraweBB7fxf25yQaVwEc3owjj/J NlVesrmWgNQt5KwRDsXrIWYgNXdyw/96G1Lr/Gds= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id 0FEB23858C54 for ; Fri, 21 Oct 2022 07:15:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0FEB23858C54 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-28-mah6xNqSPZ6wnhvuEO7icg-1; Fri, 21 Oct 2022 03:15:35 -0400 X-MC-Unique: mah6xNqSPZ6wnhvuEO7icg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 267CE185A7AA; Fri, 21 Oct 2022 07:15:35 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.193.252]) by smtp.corp.redhat.com (Postfix) with ESMTPS id DBEA42166B33; Fri, 21 Oct 2022 07:15:34 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 29L7FWag3484626 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 21 Oct 2022 09:15:32 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 29L7FVLx3484625; Fri, 21 Oct 2022 09:15:31 +0200 Date: Fri, 21 Oct 2022 09:15:31 +0200 To: Uros Bizjak Subject: [PATCH] i386: Fix up BFmode comparisons in conditional moves [PR107322] Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jakub Jelinek via Gcc-patches From: Jakub Jelinek Reply-To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747280549508822165?= X-GMAIL-MSGID: =?utf-8?q?1747280549508822165?= Hi! As the testcase shows, when cbranchbf4/cstorebf4 patterns are defined, we can get ICEs for conditional moves. The problem is that the generic conditional move expansion just calls prepare_cmp_insn which just checks that such a cbranch4 exists and returns directly such comparison and passes it down to the conditional move optabs. The following patch fixes it by punting if the comparisons aren't ix86_fp_comparison_operator (to tell the generic code it should separately compare) and to handle the promotion of BFmode comparison operands to SFmode such that comparison is performed in SFmode. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2022-10-21 Jakub Jelinek PR target/107322 * config/i386/i386-expand.cc (ix86_prepare_fp_compare_args): For BFmode comparisons promote arguments to SFmode and recurse. (ix86_expand_int_movcc, ix86_expand_fp_movcc): Return false early if comparison operands are BFmode and operands[1] is not ix86_fp_comparison_operator. * gcc.target/i386/pr107322.c: New test. Jakub --- gcc/config/i386/i386-expand.cc.jj 2022-10-19 11:20:54.602879162 +0200 +++ gcc/config/i386/i386-expand.cc 2022-10-20 12:15:37.750758679 +0200 @@ -2626,6 +2626,35 @@ ix86_prepare_fp_compare_args (enum rtx_c machine_mode op_mode = GET_MODE (op0); bool is_sse = SSE_FLOAT_MODE_SSEMATH_OR_HF_P (op_mode); + if (op_mode == BFmode) + { + rtx op = gen_lowpart (HImode, op0); + if (CONST_INT_P (op)) + op = simplify_const_unary_operation (FLOAT_EXTEND, SFmode, + op0, BFmode); + else + { + rtx t1 = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendhisi2 (t1, op)); + emit_insn (gen_ashlsi3 (t1, t1, GEN_INT (16))); + op = gen_lowpart (SFmode, t1); + } + *pop0 = op; + op = gen_lowpart (HImode, op1); + if (CONST_INT_P (op)) + op = simplify_const_unary_operation (FLOAT_EXTEND, SFmode, + op1, BFmode); + else + { + rtx t1 = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendhisi2 (t1, op)); + emit_insn (gen_ashlsi3 (t1, t1, GEN_INT (16))); + op = gen_lowpart (SFmode, t1); + } + *pop1 = op; + return ix86_prepare_fp_compare_args (code, pop0, pop1); + } + /* All of the unordered compare instructions only work on registers. The same is true of the fcomi compare instructions. The XFmode compare instructions require registers except when comparing @@ -3164,6 +3193,10 @@ ix86_expand_int_movcc (rtx operands[]) && !TARGET_64BIT)) return false; + if (GET_MODE (op0) == BFmode + && !ix86_fp_comparison_operator (operands[1], VOIDmode)) + return false; + start_sequence (); compare_op = ix86_expand_compare (code, op0, op1); compare_seq = get_insns (); @@ -4238,6 +4271,10 @@ ix86_expand_fp_movcc (rtx operands[]) rtx op0 = XEXP (operands[1], 0); rtx op1 = XEXP (operands[1], 1); + if (GET_MODE (op0) == BFmode + && !ix86_fp_comparison_operator (operands[1], VOIDmode)) + return false; + if (SSE_FLOAT_MODE_SSEMATH_OR_HF_P (mode)) { machine_mode cmode; --- gcc/testsuite/gcc.target/i386/pr107322.c.jj 2022-10-20 12:28:46.829983399 +0200 +++ gcc/testsuite/gcc.target/i386/pr107322.c 2022-10-20 12:29:44.287201650 +0200 @@ -0,0 +1,33 @@ +/* PR target/107322 */ +/* { dg-do compile } */ +/* { dg-options "-fexcess-precision=16 -O -msse2 -mfpmath=sse" } */ + +int i, j; +float k, l; +__bf16 f; + +void +foo (void) +{ + i *= 0 >= f; +} + +void +bar (void) +{ + i *= 0 <= f; +} + +void +baz (int x, int y) +{ + i = 0 >= f ? x : y; + j = 0 <= f ? x + 2 : y + 3; +} + +void +qux (float x, float y) +{ + k = 0 >= f ? x : y; + l = 0 <= f ? x + 2 : y + 3; +}