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[8.43.85.97]) by mx.google.com with ESMTPS id f16-20020a056402151000b00518286f5834si5819941edw.29.2023.06.14.04.21.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:21:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 439B33857721 for ; Wed, 14 Jun 2023 11:21:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id EB9D93858D1E for ; Wed, 14 Jun 2023 11:20:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB9D93858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1686741649tu5nqnd3 Received: from LAPTOP-EPITNQBU ( [58.60.1.5]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 14 Jun 2023 19:20:48 +0800 (CST) X-QQ-SSF: 00400000000000F0S000000A0000000 X-QQ-FEAT: tq3PnoCT2SKhbhUh8dDGjeCBrwEc2XR7ybNWLzx17BFj8qgn+GHQ51waQ5lo6 5PqRPDxSWgREXFS9nBPXH8QorFOzwTIEJQ2mTeXl/+V1B3V+YHH4q9P7QfzAuBbKGPCLj1A TVhPN0+9egniF0tR/RunA3+Uftam2mAgO+rgu6FrKjHzD3NTDVE2tDiYp6oqcKtL8W+lGXC 89L5ho/EI1XDnpVSYUyTVyTuZxNnbfN1ud8jhmZElVZIcQOvBWiZdioekAQHcXCYk3d4ZYn UTw+Yx31DPMALvdF4PNY19EGbG3nCGtMikFSyqgMMU1znyP0z8PbTnMrtNK/Eau4RwkU/3z b7MjzAVRPFMO9CONbwLFS2Aynw8R5bafmrLsP2Le/OBAoBPGi8j68RIT1Kwzmdnd/1aaV9S x+GkMiGEUqXxReEhA3w/a0Ui0V0CChfoRdDTfDjWZyg= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6081454784451573265 Date: Wed, 14 Jun 2023 19:20:49 +0800 From: "juzhe.zhong@rivai.ai" To: =?eucgb2312_cn?b?tqHA1ruq?= , gcc-patches Cc: jeffreyalaw , "Robin Dapp" , palmer Subject: =?eucgb2312_cn?b?u9i4tDogUmU6IFtQQVRDSF0gUklTQy1WOiBFbnN1cmUgdmVjdG9yIGFy?= =?eucgb2312_cn?b?Z3MgYW5kIHJldHVybiB1c2UgZnVuY3Rpb24gc3RhY2sgdG8gcGFzcyBbUFIxMTAx?= =?eucgb2312_cn?b?MTld?= References: <20230614110319.2191614-1-lehua.ding@rivai.ai>, <2023061419174452345845@rivai.ai> X-Priority: 3 X-GUID: BCC424F3-796E-4136-913D-C0F112A6E4DD X-Has-Attach: no X-Mailer: Foxmail 7.2.16.188[cn] Mime-Version: 1.0 Message-ID: X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, BODY_8BITS, CHARSET_FARAWAY_HEADER, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, KAM_SHORT, MIME_CHARSET_FARAWAY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_KAM_HTML_FONT_INVALID, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768675753180010136?= X-GMAIL-MSGID: =?utf-8?q?1768676857846895010?= Also p110119-1.c change name of test into pr110119-1.c juzhe.zhong@rivai.ai 发件人： juzhe.zhong@rivai.ai 发送时间： 2023-06-14 19:17 收件人： 丁乐华; gcc-patches 抄送： jeffreyalaw; Robin Dapp; palmer 主题： Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Oh. I see. Change if (riscv_v_ext_mode_p (arg.mode) || riscv_v_ext_tuple_mode_p (arg.mode)) into if (riscv_v_ext_mode_p (arg.mode)) since riscv_v_ext_mode_p (arg.mode) includes riscv_v_ext_vector_mode_p (arg.mode) and riscv_v_ext_tuple_mode_p (arg.mode) no need has riscv_v_ext_tuple_mode_p juzhe.zhong@rivai.ai From: Lehua Ding Date: 2023-06-14 19:03 To: gcc-patches; juzhe.zhong Subject: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] Hi, The reason for this bug is that in the case where the vector register is set to a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed through two scalar registers, but when GCC calls FUNCTION_VALUE (call function riscv_get_arg_info inside) it returns NULL_RTX. These two functions are not unified. The current treatment is to pass all vector arguments and returns through the function stack, and a new calling convention for vector registers will be added in the future. Best, Lehua PR target/110119 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode (riscv_pass_by_reference): Return true for vector mode gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/p110119-1.c: New test. * gcc.target/riscv/rvv/base/p110119-2.c: New test. --- gcc/config/riscv/riscv.cc | 19 +++++++++----- .../gcc.target/riscv/rvv/base/p110119-1.c | 26 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/p110119-2.c | 26 +++++++++++++++++++ 3 files changed, 65 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c -- 2.36.3 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dd5361c2bd2a..be868c7b6127 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3915,13 +3915,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, riscv_pass_in_vector_p (type); } - /* TODO: Currently, it will cause an ICE for --param - riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here - let GCC generate loads/stores. Ideally, we should either warn the user not - to use an RVV vector type as function argument or support the calling - convention directly. */ - if (riscv_v_ext_mode_p (mode)) + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (mode) || riscv_v_ext_tuple_mode_p (mode)) return NULL_RTX; + if (named) { riscv_aggregate_field fields[2]; @@ -4106,6 +4106,13 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) return false; } + /* All current vector arguments and return values are passed through the + function stack. Ideally, we should either warn the user not to use an RVV + vector type as function argument or support a calling convention + with better performance. */ + if (riscv_v_ext_mode_p (arg.mode) || riscv_v_ext_tuple_mode_p (arg.mode)) + return true; + /* Pass by reference if the data do not fit in two integer registers. */ return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c new file mode 100644 index 000000000000..0edbb0626299 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + return v; +} + +__attribute__ ((noipa)) vnx2qi +f_vnx2qi_2 (vnx2qi a, int8_t *out) +{ + return a; +} + +__attribute__ ((noipa)) vint32m1_t +f_vint32m1 (int8_t * a, int8_t *out) +{ + vint32m1_t v = *(vint32m1_t*)a; + return v; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c new file mode 100644 index 000000000000..b233ff1e9040 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include +#include "riscv_vector.h" + +__attribute__ ((noipa)) vint32m1x3_t +foo1 (int32_t *in, int vl) +{ + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +} + +__attribute__ ((noipa)) void +foo2 (vint32m1x3_t a, int32_t *out, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); +} + +__attribute__ ((noipa)) vint32m1x3_t +foo3 (vint32m1x3_t a, int32_t *out, int32_t *in, int vl) +{ + __riscv_vsseg3e32_v_i32m1x3 (out, a, vl); + vint32m1x3_t v = __riscv_vlseg3e32_v_i32m1x3 (in, vl); + return v; +}